424 lines
9.8 KiB
C
424 lines
9.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright © 2018 Intel Corporation
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*/
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#include <linux/sort.h>
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#include "i915_selftest.h"
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#include "intel_engine_regs.h"
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#include "intel_gpu_commands.h"
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#include "intel_gt_clock_utils.h"
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#include "selftest_engine.h"
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#include "selftest_engine_heartbeat.h"
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#include "selftests/igt_atomic.h"
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#include "selftests/igt_flush_test.h"
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#include "selftests/igt_spinner.h"
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#define COUNT 5
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static int cmp_u64(const void *A, const void *B)
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{
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const u64 *a = A, *b = B;
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return *a - *b;
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}
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static u64 trifilter(u64 *a)
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{
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sort(a, COUNT, sizeof(*a), cmp_u64, NULL);
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return (a[1] + 2 * a[2] + a[3]) >> 2;
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}
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static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value)
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{
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*cs++ = MI_SEMAPHORE_WAIT |
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MI_SEMAPHORE_GLOBAL_GTT |
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MI_SEMAPHORE_POLL |
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op;
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*cs++ = value;
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*cs++ = offset;
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*cs++ = 0;
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return cs;
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}
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static u32 *emit_store(u32 *cs, u32 offset, u32 value)
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{
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*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
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*cs++ = offset;
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*cs++ = 0;
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*cs++ = value;
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return cs;
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}
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static u32 *emit_srm(u32 *cs, i915_reg_t reg, u32 offset)
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{
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*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
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*cs++ = i915_mmio_reg_offset(reg);
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*cs++ = offset;
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*cs++ = 0;
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return cs;
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}
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static void write_semaphore(u32 *x, u32 value)
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{
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WRITE_ONCE(*x, value);
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wmb();
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}
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static int __measure_timestamps(struct intel_context *ce,
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u64 *dt, u64 *d_ring, u64 *d_ctx)
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{
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struct intel_engine_cs *engine = ce->engine;
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u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5);
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u32 offset = i915_ggtt_offset(engine->status_page.vma);
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struct i915_request *rq;
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u32 *cs;
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq))
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return PTR_ERR(rq);
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cs = intel_ring_begin(rq, 28);
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if (IS_ERR(cs)) {
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i915_request_add(rq);
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return PTR_ERR(cs);
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}
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/* Signal & wait for start */
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cs = emit_store(cs, offset + 4008, 1);
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cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_NEQ_SDD, 1);
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cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000);
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cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004);
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/* Busy wait */
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cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_EQ_SDD, 1);
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cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016);
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cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012);
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intel_ring_advance(rq, cs);
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i915_request_get(rq);
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i915_request_add(rq);
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intel_engine_flush_submission(engine);
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/* Wait for the request to start executing, that then waits for us */
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while (READ_ONCE(sema[2]) == 0)
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cpu_relax();
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/* Run the request for a 100us, sampling timestamps before/after */
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local_irq_disable();
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write_semaphore(&sema[2], 0);
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while (READ_ONCE(sema[1]) == 0) /* wait for the gpu to catch up */
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cpu_relax();
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*dt = local_clock();
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udelay(100);
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*dt = local_clock() - *dt;
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write_semaphore(&sema[2], 1);
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local_irq_enable();
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if (i915_request_wait(rq, 0, HZ / 2) < 0) {
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i915_request_put(rq);
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return -ETIME;
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}
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i915_request_put(rq);
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pr_debug("%s CTX_TIMESTAMP: [%x, %x], RING_TIMESTAMP: [%x, %x]\n",
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engine->name, sema[1], sema[3], sema[0], sema[4]);
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*d_ctx = sema[3] - sema[1];
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*d_ring = sema[4] - sema[0];
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return 0;
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}
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static int __live_engine_timestamps(struct intel_engine_cs *engine)
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{
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u64 s_ring[COUNT], s_ctx[COUNT], st[COUNT], d_ring, d_ctx, dt;
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struct intel_context *ce;
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int i, err = 0;
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ce = intel_context_create(engine);
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if (IS_ERR(ce))
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return PTR_ERR(ce);
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for (i = 0; i < COUNT; i++) {
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err = __measure_timestamps(ce, &st[i], &s_ring[i], &s_ctx[i]);
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if (err)
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break;
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}
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intel_context_put(ce);
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if (err)
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return err;
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dt = trifilter(st);
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d_ring = trifilter(s_ring);
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d_ctx = trifilter(s_ctx);
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pr_info("%s elapsed:%lldns, CTX_TIMESTAMP:%lldns, RING_TIMESTAMP:%lldns\n",
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engine->name, dt,
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intel_gt_clock_interval_to_ns(engine->gt, d_ctx),
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intel_gt_clock_interval_to_ns(engine->gt, d_ring));
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d_ring = intel_gt_clock_interval_to_ns(engine->gt, d_ring);
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if (3 * dt > 4 * d_ring || 4 * dt < 3 * d_ring) {
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pr_err("%s Mismatch between ring timestamp and walltime!\n",
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engine->name);
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return -EINVAL;
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}
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d_ring = trifilter(s_ring);
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d_ctx = trifilter(s_ctx);
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d_ctx *= engine->gt->clock_frequency;
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if (GRAPHICS_VER(engine->i915) == 11)
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d_ring *= 12500000; /* Fixed 80ns for GEN11 ctx timestamp? */
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else
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d_ring *= engine->gt->clock_frequency;
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if (3 * d_ctx > 4 * d_ring || 4 * d_ctx < 3 * d_ring) {
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pr_err("%s Mismatch between ring and context timestamps!\n",
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engine->name);
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return -EINVAL;
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}
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return 0;
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}
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static int live_engine_timestamps(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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/*
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* Check that CS_TIMESTAMP / CTX_TIMESTAMP are in sync, i.e. share
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* the same CS clock.
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*/
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if (GRAPHICS_VER(gt->i915) < 8)
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return 0;
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for_each_engine(engine, gt, id) {
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int err;
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st_engine_heartbeat_disable(engine);
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err = __live_engine_timestamps(engine);
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st_engine_heartbeat_enable(engine);
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if (err)
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return err;
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}
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return 0;
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}
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static int __spin_until_busier(struct intel_engine_cs *engine, ktime_t busyness)
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{
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ktime_t start, unused, dt;
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if (!intel_engine_uses_guc(engine))
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return 0;
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/*
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* In GuC mode of submission, the busyness stats may get updated after
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* the batch starts running. Poll for a change in busyness and timeout
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* after 500 us.
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*/
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start = ktime_get();
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while (intel_engine_get_busy_time(engine, &unused) == busyness) {
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dt = ktime_get() - start;
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if (dt > 10000000) {
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pr_err("active wait timed out %lld\n", dt);
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ENGINE_TRACE(engine, "active wait time out %lld\n", dt);
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return -ETIME;
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}
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}
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return 0;
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}
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static int live_engine_busy_stats(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct igt_spinner spin;
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int err = 0;
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/*
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* Check that if an engine supports busy-stats, they tell the truth.
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*/
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if (igt_spinner_init(&spin, gt))
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return -ENOMEM;
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GEM_BUG_ON(intel_gt_pm_is_awake(gt));
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for_each_engine(engine, gt, id) {
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struct i915_request *rq;
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ktime_t busyness, dummy;
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ktime_t de, dt;
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ktime_t t[2];
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if (!intel_engine_supports_stats(engine))
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continue;
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if (!intel_engine_can_store_dword(engine))
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continue;
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if (intel_gt_pm_wait_for_idle(gt)) {
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err = -EBUSY;
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break;
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}
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st_engine_heartbeat_disable(engine);
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ENGINE_TRACE(engine, "measuring idle time\n");
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preempt_disable();
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de = intel_engine_get_busy_time(engine, &t[0]);
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udelay(100);
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de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de);
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preempt_enable();
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dt = ktime_sub(t[1], t[0]);
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if (de < 0 || de > 10) {
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pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n",
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engine->name,
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de, (int)div64_u64(100 * de, dt), dt);
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GEM_TRACE_DUMP();
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err = -EINVAL;
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goto end;
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}
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/* 100% busy */
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rq = igt_spinner_create_request(&spin,
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engine->kernel_context,
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MI_NOOP);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto end;
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}
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i915_request_add(rq);
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busyness = intel_engine_get_busy_time(engine, &dummy);
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if (!igt_wait_for_spinner(&spin, rq)) {
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intel_gt_set_wedged(engine->gt);
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err = -ETIME;
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goto end;
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}
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err = __spin_until_busier(engine, busyness);
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if (err) {
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GEM_TRACE_DUMP();
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goto end;
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}
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ENGINE_TRACE(engine, "measuring busy time\n");
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preempt_disable();
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de = intel_engine_get_busy_time(engine, &t[0]);
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mdelay(10);
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de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de);
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preempt_enable();
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dt = ktime_sub(t[1], t[0]);
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if (100 * de < 95 * dt || 95 * de > 100 * dt) {
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pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n",
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engine->name,
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de, (int)div64_u64(100 * de, dt), dt);
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GEM_TRACE_DUMP();
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err = -EINVAL;
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goto end;
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}
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end:
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st_engine_heartbeat_enable(engine);
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igt_spinner_end(&spin);
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if (igt_flush_test(gt->i915))
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err = -EIO;
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if (err)
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break;
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}
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igt_spinner_fini(&spin);
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if (igt_flush_test(gt->i915))
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err = -EIO;
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return err;
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}
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static int live_engine_pm(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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/*
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* Check we can call intel_engine_pm_put from any context. No
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* failures are reported directly, but if we mess up lockdep should
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* tell us.
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*/
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if (intel_gt_pm_wait_for_idle(gt)) {
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pr_err("Unable to flush GT pm before test\n");
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return -EBUSY;
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}
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GEM_BUG_ON(intel_gt_pm_is_awake(gt));
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for_each_engine(engine, gt, id) {
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const typeof(*igt_atomic_phases) *p;
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for (p = igt_atomic_phases; p->name; p++) {
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/*
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* Acquisition is always synchronous, except if we
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* know that the engine is already awake, in which
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* case we should use intel_engine_pm_get_if_awake()
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* to atomically grab the wakeref.
|
||
|
|
*
|
||
|
|
* In practice,
|
||
|
|
* intel_engine_pm_get();
|
||
|
|
* intel_engine_pm_put();
|
||
|
|
* occurs in one thread, while simultaneously
|
||
|
|
* intel_engine_pm_get_if_awake();
|
||
|
|
* intel_engine_pm_put();
|
||
|
|
* occurs from atomic context in another.
|
||
|
|
*/
|
||
|
|
GEM_BUG_ON(intel_engine_pm_is_awake(engine));
|
||
|
|
intel_engine_pm_get(engine);
|
||
|
|
|
||
|
|
p->critical_section_begin();
|
||
|
|
if (!intel_engine_pm_get_if_awake(engine))
|
||
|
|
pr_err("intel_engine_pm_get_if_awake(%s) failed under %s\n",
|
||
|
|
engine->name, p->name);
|
||
|
|
else
|
||
|
|
intel_engine_pm_put_async(engine);
|
||
|
|
intel_engine_pm_put_async(engine);
|
||
|
|
p->critical_section_end();
|
||
|
|
|
||
|
|
intel_engine_pm_flush(engine);
|
||
|
|
|
||
|
|
if (intel_engine_pm_is_awake(engine)) {
|
||
|
|
pr_err("%s is still awake after flushing pm\n",
|
||
|
|
engine->name);
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* gt wakeref is async (deferred to workqueue) */
|
||
|
|
if (intel_gt_pm_wait_for_idle(gt)) {
|
||
|
|
pr_err("GT failed to idle\n");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int live_engine_pm_selftests(struct intel_gt *gt)
|
||
|
|
{
|
||
|
|
static const struct i915_subtest tests[] = {
|
||
|
|
SUBTEST(live_engine_timestamps),
|
||
|
|
SUBTEST(live_engine_busy_stats),
|
||
|
|
SUBTEST(live_engine_pm),
|
||
|
|
};
|
||
|
|
|
||
|
|
return intel_gt_live_subtests(tests, gt);
|
||
|
|
}
|