82 lines
2.8 KiB
C
82 lines
2.8 KiB
C
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_GMBUS_REGS_H__
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#define __INTEL_GMBUS_REGS_H__
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#include "i915_reg_defs.h"
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#define GMBUS_MMIO_BASE(__i915) ((__i915)->display.gmbus.mmio_base)
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#define GPIO(__i915, gpio) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5010 + 4 * (gpio))
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#define GPIO_CLOCK_DIR_MASK (1 << 0)
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#define GPIO_CLOCK_DIR_IN (0 << 1)
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#define GPIO_CLOCK_DIR_OUT (1 << 1)
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#define GPIO_CLOCK_VAL_MASK (1 << 2)
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#define GPIO_CLOCK_VAL_OUT (1 << 3)
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#define GPIO_CLOCK_VAL_IN (1 << 4)
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#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
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#define GPIO_DATA_DIR_MASK (1 << 8)
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#define GPIO_DATA_DIR_IN (0 << 9)
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#define GPIO_DATA_DIR_OUT (1 << 9)
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#define GPIO_DATA_VAL_MASK (1 << 10)
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#define GPIO_DATA_VAL_OUT (1 << 11)
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#define GPIO_DATA_VAL_IN (1 << 12)
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#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
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/* clock/port select */
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#define GMBUS0(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5100)
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#define GMBUS_AKSV_SELECT (1 << 11)
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#define GMBUS_RATE_100KHZ (0 << 8)
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#define GMBUS_RATE_50KHZ (1 << 8)
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#define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */
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#define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
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#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
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#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
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/* command/status */
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#define GMBUS1(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5104)
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#define GMBUS_SW_CLR_INT (1 << 31)
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#define GMBUS_SW_RDY (1 << 30)
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#define GMBUS_ENT (1 << 29) /* enable timeout */
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#define GMBUS_CYCLE_NONE (0 << 25)
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#define GMBUS_CYCLE_WAIT (1 << 25)
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#define GMBUS_CYCLE_INDEX (2 << 25)
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#define GMBUS_CYCLE_STOP (4 << 25)
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#define GMBUS_BYTE_COUNT_SHIFT 16
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#define GMBUS_BYTE_COUNT_MAX 256U
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#define GEN9_GMBUS_BYTE_COUNT_MAX 511U
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#define GMBUS_SLAVE_INDEX_SHIFT 8
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#define GMBUS_SLAVE_ADDR_SHIFT 1
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#define GMBUS_SLAVE_READ (1 << 0)
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#define GMBUS_SLAVE_WRITE (0 << 0)
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/* status */
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#define GMBUS2(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5108)
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#define GMBUS_INUSE (1 << 15)
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#define GMBUS_HW_WAIT_PHASE (1 << 14)
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#define GMBUS_STALL_TIMEOUT (1 << 13)
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#define GMBUS_INT (1 << 12)
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#define GMBUS_HW_RDY (1 << 11)
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#define GMBUS_SATOER (1 << 10)
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#define GMBUS_ACTIVE (1 << 9)
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/* data buffer bytes 3-0 */
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#define GMBUS3(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x510c)
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/* interrupt mask (Pineview+) */
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#define GMBUS4(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5110)
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#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
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#define GMBUS_NAK_EN (1 << 3)
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#define GMBUS_IDLE_EN (1 << 2)
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#define GMBUS_HW_WAIT_EN (1 << 1)
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#define GMBUS_HW_RDY_EN (1 << 0)
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/* byte index */
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#define GMBUS5(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5120)
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#define GMBUS_2BYTE_INDEX_EN (1 << 31)
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#endif /* __INTEL_GMBUS_REGS_H__ */
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