114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* ST stm32 Chrom-Art - 2D Graphics Accelerator Driver
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*
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* Copyright (c) 2021 Dillon Min
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* Dillon Min, <dillon.minfei@gmail.com>
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*
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* based on s5p-g2d
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* Kamil Debski, <k.debski@samsung.com>
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*/
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#ifndef __DMA2D_REGS_H__
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#define __DMA2D_REGS_H__
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#define DMA2D_CR_REG 0x0000
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#define CR_MODE_MASK GENMASK(17, 16)
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#define CR_MODE_SHIFT 16
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#define CR_M2M 0x0000
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#define CR_M2M_PFC BIT(16)
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#define CR_M2M_BLEND BIT(17)
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#define CR_R2M (BIT(17) | BIT(16))
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#define CR_CEIE BIT(13)
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#define CR_CTCIE BIT(12)
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#define CR_CAEIE BIT(11)
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#define CR_TWIE BIT(10)
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#define CR_TCIE BIT(9)
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#define CR_TEIE BIT(8)
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#define CR_ABORT BIT(2)
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#define CR_SUSP BIT(1)
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#define CR_START BIT(0)
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#define DMA2D_ISR_REG 0x0004
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#define ISR_CEIF BIT(5)
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#define ISR_CTCIF BIT(4)
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#define ISR_CAEIF BIT(3)
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#define ISR_TWIF BIT(2)
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#define ISR_TCIF BIT(1)
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#define ISR_TEIF BIT(0)
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#define DMA2D_IFCR_REG 0x0008
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#define IFCR_CCEIF BIT(5)
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#define IFCR_CCTCIF BIT(4)
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#define IFCR_CAECIF BIT(3)
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#define IFCR_CTWIF BIT(2)
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#define IFCR_CTCIF BIT(1)
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#define IFCR_CTEIF BIT(0)
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#define DMA2D_FGMAR_REG 0x000c
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#define DMA2D_FGOR_REG 0x0010
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#define FGOR_LO_MASK GENMASK(13, 0)
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#define DMA2D_BGMAR_REG 0x0014
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#define DMA2D_BGOR_REG 0x0018
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#define BGOR_LO_MASK GENMASK(13, 0)
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#define DMA2D_FGPFCCR_REG 0x001c
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#define FGPFCCR_ALPHA_MASK GENMASK(31, 24)
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#define FGPFCCR_AM_MASK GENMASK(17, 16)
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#define FGPFCCR_CS_MASK GENMASK(15, 8)
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#define FGPFCCR_START BIT(5)
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#define FGPFCCR_CCM_RGB888 BIT(4)
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#define FGPFCCR_CM_MASK GENMASK(3, 0)
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#define DMA2D_FGCOLR_REG 0x0020
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#define FGCOLR_REG_MASK GENMASK(23, 16)
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#define FGCOLR_GREEN_MASK GENMASK(15, 8)
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#define FGCOLR_BLUE_MASK GENMASK(7, 0)
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#define DMA2D_BGPFCCR_REG 0x0024
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#define BGPFCCR_ALPHA_MASK GENMASK(31, 24)
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#define BGPFCCR_AM_MASK GENMASK(17, 16)
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#define BGPFCCR_CS_MASK GENMASK(15, 8)
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#define BGPFCCR_START BIT(5)
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#define BGPFCCR_CCM_RGB888 BIT(4)
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#define BGPFCCR_CM_MASK GENMASK(3, 0)
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#define DMA2D_BGCOLR_REG 0x0028
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#define BGCOLR_REG_MASK GENMASK(23, 16)
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#define BGCOLR_GREEN_MASK GENMASK(15, 8)
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#define BGCOLR_BLUE_MASK GENMASK(7, 0)
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#define DMA2D_OPFCCR_REG 0x0034
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#define OPFCCR_CM_MASK GENMASK(2, 0)
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#define DMA2D_OCOLR_REG 0x0038
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#define OCOLR_ALPHA_MASK GENMASK(31, 24)
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#define OCOLR_RED_MASK GENMASK(23, 16)
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#define OCOLR_GREEN_MASK GENMASK(15, 8)
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#define OCOLR_BLUE_MASK GENMASK(7, 0)
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#define DMA2D_OMAR_REG 0x003c
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#define DMA2D_OOR_REG 0x0040
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#define OOR_LO_MASK GENMASK(13, 0)
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#define DMA2D_NLR_REG 0x0044
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#define NLR_PL_MASK GENMASK(29, 16)
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#define NLR_NL_MASK GENMASK(15, 0)
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/* Hardware limits */
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#define MAX_WIDTH 2592
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#define MAX_HEIGHT 2592
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#define DEFAULT_WIDTH 240
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#define DEFAULT_HEIGHT 320
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#define DEFAULT_SIZE 307200
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#define CM_MODE_ARGB8888 0x00
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#define CM_MODE_ARGB4444 0x04
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#define CM_MODE_A4 0x0a
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#endif /* __DMA2D_REGS_H__ */
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