107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* Copyright (C) 2010 John Crispin <john@phrozen.org>
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*/
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#ifndef _LTQ_XWAY_H__
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#define _LTQ_XWAY_H__
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#ifdef CONFIG_SOC_TYPE_XWAY
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#include <lantiq.h>
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/* Chip IDs */
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#define SOC_ID_DANUBE1 0x129
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#define SOC_ID_DANUBE2 0x12B
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#define SOC_ID_TWINPASS 0x12D
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#define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */
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#define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */
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#define SOC_ID_ARX188 0x16C
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#define SOC_ID_ARX168_1 0x16D
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#define SOC_ID_ARX168_2 0x16E
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#define SOC_ID_ARX182 0x16F
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#define SOC_ID_GRX188 0x170
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#define SOC_ID_GRX168 0x171
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#define SOC_ID_VRX288 0x1C0 /* v1.1 */
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#define SOC_ID_VRX282 0x1C1 /* v1.1 */
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#define SOC_ID_VRX268 0x1C2 /* v1.1 */
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#define SOC_ID_GRX268 0x1C8 /* v1.1 */
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#define SOC_ID_GRX288 0x1C9 /* v1.1 */
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#define SOC_ID_VRX288_2 0x00B /* v1.2 */
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#define SOC_ID_VRX268_2 0x00C /* v1.2 */
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#define SOC_ID_GRX288_2 0x00D /* v1.2 */
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#define SOC_ID_GRX282_2 0x00E /* v1.2 */
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#define SOC_ID_VRX220 0x000
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#define SOC_ID_ARX362 0x004
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#define SOC_ID_ARX368 0x005
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#define SOC_ID_ARX382 0x007
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#define SOC_ID_ARX388 0x008
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#define SOC_ID_URX388 0x009
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#define SOC_ID_GRX383 0x010
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#define SOC_ID_GRX369 0x011
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#define SOC_ID_GRX387 0x00F
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#define SOC_ID_GRX389 0x012
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/* SoC Types */
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#define SOC_TYPE_DANUBE 0x01
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#define SOC_TYPE_TWINPASS 0x02
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#define SOC_TYPE_AR9 0x03
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#define SOC_TYPE_VR9 0x04 /* v1.1 */
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#define SOC_TYPE_VR9_2 0x05 /* v1.2 */
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#define SOC_TYPE_AMAZON_SE 0x06
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#define SOC_TYPE_AR10 0x07
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#define SOC_TYPE_GRX390 0x08
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#define SOC_TYPE_VRX220 0x09
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/* BOOT_SEL - find what boot media we have */
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#define BS_EXT_ROM 0x0
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#define BS_FLASH 0x1
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#define BS_MII0 0x2
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#define BS_PCI 0x3
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#define BS_UART1 0x4
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#define BS_SPI 0x5
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#define BS_NAND 0x6
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#define BS_RMII0 0x7
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/* helpers used to access the cgu */
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#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
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#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
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extern __iomem void *ltq_cgu_membase;
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/*
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* during early_printk no ioremap is possible
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* let's use KSEG1 instead
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*/
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#define LTQ_ASC1_BASE_ADDR 0x1E100C00
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#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
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/* EBU - external bus unit */
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#define LTQ_EBU_BUSCON0 0x0060
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#define LTQ_EBU_PCC_CON 0x0090
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#define LTQ_EBU_PCC_IEN 0x00A4
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#define LTQ_EBU_PCC_ISTAT 0x00A0
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#define LTQ_EBU_BUSCON1 0x0064
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#define LTQ_EBU_ADDRSEL1 0x0024
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#define EBU_WRDIS 0x80000000
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/* WDT */
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#define LTQ_RST_CAUSE_WDTRST 0x20
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/* MPS - multi processor unit (voice) */
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#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
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#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
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/* allow booting xrx200 phys */
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int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
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/* request a non-gpio and set the PIO config */
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#define PMU_PPE BIT(13)
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extern void ltq_pmu_enable(unsigned int module);
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extern void ltq_pmu_disable(unsigned int module);
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#endif /* CONFIG_SOC_TYPE_XWAY */
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#endif /* _LTQ_XWAY_H__ */
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