57 lines
1.6 KiB
YAML
57 lines
1.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/mscc,vsc7514-serdes.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microsemi Ocelot SerDes muxing
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maintainers:
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- Alexandre Belloni <alexandre.belloni@bootlin.com>
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- UNGLinuxDriver@microchip.com
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description: |
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On Microsemi Ocelot, there is a handful of registers in HSIO address
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space for setting up the SerDes to switch port muxing.
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A SerDes X can be "muxed" to work with switch port Y or Z for example.
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One specific SerDes can also be used as a PCIe interface.
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Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
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There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
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half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
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10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
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Also, SERDES6G number (aka "macro") 0 is the only interface supporting
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QSGMII.
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This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
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Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot.
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properties:
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compatible:
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enum:
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- mscc,vsc7514-serdes
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"#phy-cells":
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const: 2
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description: |
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The first number defines the input port to use for a given SerDes macro.
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The second defines the macro to use. They are defined in
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dt-bindings/phy/phy-ocelot-serdes.h
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required:
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- compatible
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- "#phy-cells"
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additionalProperties:
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false
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examples:
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- |
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serdes: serdes {
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compatible = "mscc,vsc7514-serdes";
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#phy-cells = <2>;
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};
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