757 lines
30 KiB
C++
757 lines
30 KiB
C++
//===--- ARM.cpp - ARM (not AArch64) Helpers for Tools ----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "clang/Driver/Driver.h"
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#include "clang/Driver/DriverDiagnostic.h"
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#include "clang/Driver/Options.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/Option/ArgList.h"
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#include "llvm/Support/TargetParser.h"
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#include "llvm/Support/Host.h"
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using namespace clang::driver;
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using namespace clang::driver::tools;
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using namespace clang;
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using namespace llvm::opt;
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// Get SubArch (vN).
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int arm::getARMSubArchVersionNumber(const llvm::Triple &Triple) {
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llvm::StringRef Arch = Triple.getArchName();
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return llvm::ARM::parseArchVersion(Arch);
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}
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// True if M-profile.
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bool arm::isARMMProfile(const llvm::Triple &Triple) {
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llvm::StringRef Arch = Triple.getArchName();
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return llvm::ARM::parseArchProfile(Arch) == llvm::ARM::ProfileKind::M;
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}
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// True if A-profile.
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bool arm::isARMAProfile(const llvm::Triple &Triple) {
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llvm::StringRef Arch = Triple.getArchName();
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return llvm::ARM::parseArchProfile(Arch) == llvm::ARM::ProfileKind::A;
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}
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// Get Arch/CPU from args.
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void arm::getARMArchCPUFromArgs(const ArgList &Args, llvm::StringRef &Arch,
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llvm::StringRef &CPU, bool FromAs) {
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if (const Arg *A = Args.getLastArg(clang::driver::options::OPT_mcpu_EQ))
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CPU = A->getValue();
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if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
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Arch = A->getValue();
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if (!FromAs)
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return;
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for (const Arg *A :
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Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler)) {
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StringRef Value = A->getValue();
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if (Value.startswith("-mcpu="))
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CPU = Value.substr(6);
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if (Value.startswith("-march="))
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Arch = Value.substr(7);
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}
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}
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// Handle -mhwdiv=.
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// FIXME: Use ARMTargetParser.
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static void getARMHWDivFeatures(const Driver &D, const Arg *A,
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const ArgList &Args, StringRef HWDiv,
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std::vector<StringRef> &Features) {
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uint64_t HWDivID = llvm::ARM::parseHWDiv(HWDiv);
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if (!llvm::ARM::getHWDivFeatures(HWDivID, Features))
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D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
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}
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// Handle -mfpu=.
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static unsigned getARMFPUFeatures(const Driver &D, const Arg *A,
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const ArgList &Args, StringRef FPU,
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std::vector<StringRef> &Features) {
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unsigned FPUID = llvm::ARM::parseFPU(FPU);
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if (!llvm::ARM::getFPUFeatures(FPUID, Features))
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D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
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return FPUID;
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}
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// Decode ARM features from string like +[no]featureA+[no]featureB+...
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static bool DecodeARMFeatures(const Driver &D, StringRef text, StringRef CPU,
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llvm::ARM::ArchKind ArchKind,
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std::vector<StringRef> &Features,
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unsigned &ArgFPUID) {
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SmallVector<StringRef, 8> Split;
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text.split(Split, StringRef("+"), -1, false);
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for (StringRef Feature : Split) {
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if (!appendArchExtFeatures(CPU, ArchKind, Feature, Features, ArgFPUID))
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return false;
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}
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return true;
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}
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static void DecodeARMFeaturesFromCPU(const Driver &D, StringRef CPU,
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std::vector<StringRef> &Features) {
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CPU = CPU.split("+").first;
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if (CPU != "generic") {
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llvm::ARM::ArchKind ArchKind = llvm::ARM::parseCPUArch(CPU);
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uint64_t Extension = llvm::ARM::getDefaultExtensions(CPU, ArchKind);
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llvm::ARM::getExtensionFeatures(Extension, Features);
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}
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}
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// Check if -march is valid by checking if it can be canonicalised and parsed.
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// getARMArch is used here instead of just checking the -march value in order
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// to handle -march=native correctly.
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static void checkARMArchName(const Driver &D, const Arg *A, const ArgList &Args,
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llvm::StringRef ArchName, llvm::StringRef CPUName,
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std::vector<StringRef> &Features,
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const llvm::Triple &Triple, unsigned &ArgFPUID) {
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std::pair<StringRef, StringRef> Split = ArchName.split("+");
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std::string MArch = arm::getARMArch(ArchName, Triple);
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llvm::ARM::ArchKind ArchKind = llvm::ARM::parseArch(MArch);
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if (ArchKind == llvm::ARM::ArchKind::INVALID ||
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(Split.second.size() && !DecodeARMFeatures(D, Split.second, CPUName,
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ArchKind, Features, ArgFPUID)))
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D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
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}
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// Check -mcpu=. Needs ArchName to handle -mcpu=generic.
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static void checkARMCPUName(const Driver &D, const Arg *A, const ArgList &Args,
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llvm::StringRef CPUName, llvm::StringRef ArchName,
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std::vector<StringRef> &Features,
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const llvm::Triple &Triple, unsigned &ArgFPUID) {
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std::pair<StringRef, StringRef> Split = CPUName.split("+");
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std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
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llvm::ARM::ArchKind ArchKind =
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arm::getLLVMArchKindForARM(CPU, ArchName, Triple);
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if (ArchKind == llvm::ARM::ArchKind::INVALID ||
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(Split.second.size() &&
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!DecodeARMFeatures(D, Split.second, CPU, ArchKind, Features, ArgFPUID)))
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D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
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}
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bool arm::useAAPCSForMachO(const llvm::Triple &T) {
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// The backend is hardwired to assume AAPCS for M-class processors, ensure
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// the frontend matches that.
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return T.getEnvironment() == llvm::Triple::EABI ||
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T.getEnvironment() == llvm::Triple::EABIHF ||
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T.getOS() == llvm::Triple::UnknownOS || isARMMProfile(T);
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}
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// Select mode for reading thread pointer (-mtp=soft/cp15).
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arm::ReadTPMode arm::getReadTPMode(const Driver &D, const ArgList &Args) {
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if (Arg *A = Args.getLastArg(options::OPT_mtp_mode_EQ)) {
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arm::ReadTPMode ThreadPointer =
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llvm::StringSwitch<arm::ReadTPMode>(A->getValue())
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.Case("cp15", ReadTPMode::Cp15)
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.Case("soft", ReadTPMode::Soft)
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.Default(ReadTPMode::Invalid);
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if (ThreadPointer != ReadTPMode::Invalid)
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return ThreadPointer;
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if (StringRef(A->getValue()).empty())
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D.Diag(diag::err_drv_missing_arg_mtp) << A->getAsString(Args);
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else
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D.Diag(diag::err_drv_invalid_mtp) << A->getAsString(Args);
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return ReadTPMode::Invalid;
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}
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return ReadTPMode::Soft;
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}
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arm::FloatABI arm::getARMFloatABI(const ToolChain &TC, const ArgList &Args) {
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return arm::getARMFloatABI(TC.getDriver(), TC.getEffectiveTriple(), Args);
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}
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arm::FloatABI arm::getDefaultFloatABI(const llvm::Triple &Triple) {
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auto SubArch = getARMSubArchVersionNumber(Triple);
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switch (Triple.getOS()) {
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case llvm::Triple::Darwin:
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case llvm::Triple::MacOSX:
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case llvm::Triple::IOS:
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case llvm::Triple::TvOS:
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// Darwin defaults to "softfp" for v6 and v7.
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if (Triple.isWatchABI())
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return FloatABI::Hard;
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else
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return (SubArch == 6 || SubArch == 7) ? FloatABI::SoftFP : FloatABI::Soft;
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case llvm::Triple::WatchOS:
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return FloatABI::Hard;
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// FIXME: this is invalid for WindowsCE
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case llvm::Triple::Win32:
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return FloatABI::Hard;
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case llvm::Triple::NetBSD:
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switch (Triple.getEnvironment()) {
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case llvm::Triple::EABIHF:
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case llvm::Triple::GNUEABIHF:
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return FloatABI::Hard;
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default:
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return FloatABI::Soft;
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}
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break;
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case llvm::Triple::FreeBSD:
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switch (Triple.getEnvironment()) {
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case llvm::Triple::GNUEABIHF:
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return FloatABI::Hard;
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default:
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// FreeBSD defaults to soft float
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return FloatABI::Soft;
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}
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break;
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case llvm::Triple::OpenBSD:
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return FloatABI::SoftFP;
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default:
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switch (Triple.getEnvironment()) {
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case llvm::Triple::GNUEABIHF:
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case llvm::Triple::MuslEABIHF:
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case llvm::Triple::EABIHF:
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return FloatABI::Hard;
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case llvm::Triple::GNUEABI:
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case llvm::Triple::MuslEABI:
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case llvm::Triple::EABI:
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// EABI is always AAPCS, and if it was not marked 'hard', it's softfp
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return FloatABI::SoftFP;
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case llvm::Triple::Android:
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return (SubArch >= 7) ? FloatABI::SoftFP : FloatABI::Soft;
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default:
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return FloatABI::Invalid;
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}
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}
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return FloatABI::Invalid;
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}
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// Select the float ABI as determined by -msoft-float, -mhard-float, and
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// -mfloat-abi=.
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arm::FloatABI arm::getARMFloatABI(const Driver &D, const llvm::Triple &Triple,
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const ArgList &Args) {
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arm::FloatABI ABI = FloatABI::Invalid;
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if (Arg *A =
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Args.getLastArg(options::OPT_msoft_float, options::OPT_mhard_float,
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options::OPT_mfloat_abi_EQ)) {
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if (A->getOption().matches(options::OPT_msoft_float)) {
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ABI = FloatABI::Soft;
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} else if (A->getOption().matches(options::OPT_mhard_float)) {
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ABI = FloatABI::Hard;
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} else {
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ABI = llvm::StringSwitch<arm::FloatABI>(A->getValue())
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.Case("soft", FloatABI::Soft)
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.Case("softfp", FloatABI::SoftFP)
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.Case("hard", FloatABI::Hard)
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.Default(FloatABI::Invalid);
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if (ABI == FloatABI::Invalid && !StringRef(A->getValue()).empty()) {
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D.Diag(diag::err_drv_invalid_mfloat_abi) << A->getAsString(Args);
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ABI = FloatABI::Soft;
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}
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}
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}
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// If unspecified, choose the default based on the platform.
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if (ABI == FloatABI::Invalid)
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ABI = arm::getDefaultFloatABI(Triple);
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if (ABI == FloatABI::Invalid) {
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// Assume "soft", but warn the user we are guessing.
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if (Triple.isOSBinFormatMachO() &&
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Triple.getSubArch() == llvm::Triple::ARMSubArch_v7em)
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ABI = FloatABI::Hard;
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else
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ABI = FloatABI::Soft;
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if (Triple.getOS() != llvm::Triple::UnknownOS ||
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!Triple.isOSBinFormatMachO())
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D.Diag(diag::warn_drv_assuming_mfloat_abi_is) << "soft";
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}
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assert(ABI != FloatABI::Invalid && "must select an ABI");
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return ABI;
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}
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static bool hasIntegerMVE(const std::vector<StringRef> &F) {
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auto MVE = llvm::find(llvm::reverse(F), "+mve");
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auto NoMVE = llvm::find(llvm::reverse(F), "-mve");
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return MVE != F.rend() &&
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(NoMVE == F.rend() || std::distance(MVE, NoMVE) > 0);
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}
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void arm::getARMTargetFeatures(const Driver &D, const llvm::Triple &Triple,
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const ArgList &Args, ArgStringList &CmdArgs,
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std::vector<StringRef> &Features, bool ForAS) {
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bool KernelOrKext =
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Args.hasArg(options::OPT_mkernel, options::OPT_fapple_kext);
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arm::FloatABI ABI = arm::getARMFloatABI(D, Triple, Args);
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arm::ReadTPMode ThreadPointer = arm::getReadTPMode(D, Args);
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const Arg *WaCPU = nullptr, *WaFPU = nullptr;
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const Arg *WaHDiv = nullptr, *WaArch = nullptr;
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// This vector will accumulate features from the architecture
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// extension suffixes on -mcpu and -march (e.g. the 'bar' in
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// -mcpu=foo+bar). We want to apply those after the features derived
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// from the FPU, in case -mfpu generates a negative feature which
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// the +bar is supposed to override.
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std::vector<StringRef> ExtensionFeatures;
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if (!ForAS) {
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// FIXME: Note, this is a hack, the LLVM backend doesn't actually use these
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// yet (it uses the -mfloat-abi and -msoft-float options), and it is
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// stripped out by the ARM target. We should probably pass this a new
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// -target-option, which is handled by the -cc1/-cc1as invocation.
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//
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// FIXME2: For consistency, it would be ideal if we set up the target
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// machine state the same when using the frontend or the assembler. We don't
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// currently do that for the assembler, we pass the options directly to the
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// backend and never even instantiate the frontend TargetInfo. If we did,
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// and used its handleTargetFeatures hook, then we could ensure the
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// assembler and the frontend behave the same.
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// Use software floating point operations?
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if (ABI == arm::FloatABI::Soft)
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Features.push_back("+soft-float");
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// Use software floating point argument passing?
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if (ABI != arm::FloatABI::Hard)
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Features.push_back("+soft-float-abi");
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} else {
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// Here, we make sure that -Wa,-mfpu/cpu/arch/hwdiv will be passed down
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// to the assembler correctly.
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for (const Arg *A :
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Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler)) {
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StringRef Value = A->getValue();
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if (Value.startswith("-mfpu=")) {
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WaFPU = A;
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} else if (Value.startswith("-mcpu=")) {
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WaCPU = A;
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} else if (Value.startswith("-mhwdiv=")) {
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WaHDiv = A;
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} else if (Value.startswith("-march=")) {
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WaArch = A;
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}
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}
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}
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if (ThreadPointer == arm::ReadTPMode::Cp15)
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Features.push_back("+read-tp-hard");
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const Arg *ArchArg = Args.getLastArg(options::OPT_march_EQ);
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const Arg *CPUArg = Args.getLastArg(options::OPT_mcpu_EQ);
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StringRef ArchName;
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StringRef CPUName;
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unsigned ArchArgFPUID = llvm::ARM::FK_INVALID;
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unsigned CPUArgFPUID = llvm::ARM::FK_INVALID;
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// Check -mcpu. ClangAs gives preference to -Wa,-mcpu=.
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if (WaCPU) {
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if (CPUArg)
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D.Diag(clang::diag::warn_drv_unused_argument)
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<< CPUArg->getAsString(Args);
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CPUName = StringRef(WaCPU->getValue()).substr(6);
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CPUArg = WaCPU;
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} else if (CPUArg)
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CPUName = CPUArg->getValue();
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// Check -march. ClangAs gives preference to -Wa,-march=.
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if (WaArch) {
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if (ArchArg)
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D.Diag(clang::diag::warn_drv_unused_argument)
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<< ArchArg->getAsString(Args);
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ArchName = StringRef(WaArch->getValue()).substr(7);
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checkARMArchName(D, WaArch, Args, ArchName, CPUName, ExtensionFeatures,
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Triple, ArchArgFPUID);
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// FIXME: Set Arch.
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D.Diag(clang::diag::warn_drv_unused_argument) << WaArch->getAsString(Args);
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} else if (ArchArg) {
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ArchName = ArchArg->getValue();
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checkARMArchName(D, ArchArg, Args, ArchName, CPUName, ExtensionFeatures,
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Triple, ArchArgFPUID);
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}
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// Add CPU features for generic CPUs
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if (CPUName == "native") {
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llvm::StringMap<bool> HostFeatures;
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if (llvm::sys::getHostCPUFeatures(HostFeatures))
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for (auto &F : HostFeatures)
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Features.push_back(
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Args.MakeArgString((F.second ? "+" : "-") + F.first()));
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} else if (!CPUName.empty()) {
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// This sets the default features for the specified CPU. We certainly don't
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// want to override the features that have been explicitly specified on the
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// command line. Therefore, process them directly instead of appending them
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// at the end later.
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DecodeARMFeaturesFromCPU(D, CPUName, Features);
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}
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if (CPUArg)
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checkARMCPUName(D, CPUArg, Args, CPUName, ArchName, ExtensionFeatures,
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Triple, CPUArgFPUID);
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// Honor -mfpu=. ClangAs gives preference to -Wa,-mfpu=.
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unsigned FPUID = llvm::ARM::FK_INVALID;
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const Arg *FPUArg = Args.getLastArg(options::OPT_mfpu_EQ);
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if (WaFPU) {
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if (FPUArg)
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D.Diag(clang::diag::warn_drv_unused_argument)
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<< FPUArg->getAsString(Args);
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(void)getARMFPUFeatures(D, WaFPU, Args, StringRef(WaFPU->getValue()).substr(6),
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Features);
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} else if (FPUArg) {
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FPUID = getARMFPUFeatures(D, FPUArg, Args, FPUArg->getValue(), Features);
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} else if (Triple.isAndroid() && getARMSubArchVersionNumber(Triple) >= 7) {
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const char *AndroidFPU = "neon";
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FPUID = llvm::ARM::parseFPU(AndroidFPU);
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if (!llvm::ARM::getFPUFeatures(FPUID, Features))
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D.Diag(clang::diag::err_drv_clang_unsupported)
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<< std::string("-mfpu=") + AndroidFPU;
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}
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// Now we've finished accumulating features from arch, cpu and fpu,
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// we can append the ones for architecture extensions that we
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// collected separately.
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Features.insert(std::end(Features),
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std::begin(ExtensionFeatures), std::end(ExtensionFeatures));
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// Honor -mhwdiv=. ClangAs gives preference to -Wa,-mhwdiv=.
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const Arg *HDivArg = Args.getLastArg(options::OPT_mhwdiv_EQ);
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if (WaHDiv) {
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if (HDivArg)
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D.Diag(clang::diag::warn_drv_unused_argument)
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<< HDivArg->getAsString(Args);
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getARMHWDivFeatures(D, WaHDiv, Args,
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StringRef(WaHDiv->getValue()).substr(8), Features);
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} else if (HDivArg)
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getARMHWDivFeatures(D, HDivArg, Args, HDivArg->getValue(), Features);
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// Handle (arch-dependent) fp16fml/fullfp16 relationship.
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// Must happen before any features are disabled due to soft-float.
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// FIXME: this fp16fml option handling will be reimplemented after the
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// TargetParser rewrite.
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const auto ItRNoFullFP16 = std::find(Features.rbegin(), Features.rend(), "-fullfp16");
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const auto ItRFP16FML = std::find(Features.rbegin(), Features.rend(), "+fp16fml");
|
|
if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8_4a) {
|
|
const auto ItRFullFP16 = std::find(Features.rbegin(), Features.rend(), "+fullfp16");
|
|
if (ItRFullFP16 < ItRNoFullFP16 && ItRFullFP16 < ItRFP16FML) {
|
|
// Only entangled feature that can be to the right of this +fullfp16 is -fp16fml.
|
|
// Only append the +fp16fml if there is no -fp16fml after the +fullfp16.
|
|
if (std::find(Features.rbegin(), ItRFullFP16, "-fp16fml") == ItRFullFP16)
|
|
Features.push_back("+fp16fml");
|
|
}
|
|
else
|
|
goto fp16_fml_fallthrough;
|
|
}
|
|
else {
|
|
fp16_fml_fallthrough:
|
|
// In both of these cases, putting the 'other' feature on the end of the vector will
|
|
// result in the same effect as placing it immediately after the current feature.
|
|
if (ItRNoFullFP16 < ItRFP16FML)
|
|
Features.push_back("-fp16fml");
|
|
else if (ItRNoFullFP16 > ItRFP16FML)
|
|
Features.push_back("+fullfp16");
|
|
}
|
|
|
|
// Setting -msoft-float/-mfloat-abi=soft, -mfpu=none, or adding +nofp to
|
|
// -march/-mcpu effectively disables the FPU (GCC ignores the -mfpu options in
|
|
// this case). Note that the ABI can also be set implicitly by the target
|
|
// selected.
|
|
if (ABI == arm::FloatABI::Soft) {
|
|
llvm::ARM::getFPUFeatures(llvm::ARM::FK_NONE, Features);
|
|
|
|
// Disable all features relating to hardware FP, not already disabled by the
|
|
// above call.
|
|
Features.insert(Features.end(), {"-dotprod", "-fp16fml", "-bf16", "-mve",
|
|
"-mve.fp", "-fpregs"});
|
|
} else if (FPUID == llvm::ARM::FK_NONE ||
|
|
ArchArgFPUID == llvm::ARM::FK_NONE ||
|
|
CPUArgFPUID == llvm::ARM::FK_NONE) {
|
|
// -mfpu=none, -march=armvX+nofp or -mcpu=X+nofp is *very* similar to
|
|
// -mfloat-abi=soft, only that it should not disable MVE-I. They disable the
|
|
// FPU, but not the FPU registers, thus MVE-I, which depends only on the
|
|
// latter, is still supported.
|
|
Features.insert(Features.end(),
|
|
{"-dotprod", "-fp16fml", "-bf16", "-mve.fp"});
|
|
if (!hasIntegerMVE(Features))
|
|
Features.emplace_back("-fpregs");
|
|
}
|
|
|
|
// En/disable crc code generation.
|
|
if (Arg *A = Args.getLastArg(options::OPT_mcrc, options::OPT_mnocrc)) {
|
|
if (A->getOption().matches(options::OPT_mcrc))
|
|
Features.push_back("+crc");
|
|
else
|
|
Features.push_back("-crc");
|
|
}
|
|
|
|
// For Arch >= ARMv8.0 && A profile: crypto = sha2 + aes
|
|
// FIXME: this needs reimplementation after the TargetParser rewrite
|
|
auto CryptoIt = llvm::find_if(llvm::reverse(Features), [](const StringRef F) {
|
|
return F.contains("crypto");
|
|
});
|
|
if (CryptoIt != Features.rend()) {
|
|
if (CryptoIt->take_front() == "+") {
|
|
StringRef ArchSuffix = arm::getLLVMArchSuffixForARM(
|
|
arm::getARMTargetCPU(CPUName, ArchName, Triple), ArchName, Triple);
|
|
if (llvm::ARM::parseArchVersion(ArchSuffix) >= 8 &&
|
|
llvm::ARM::parseArchProfile(ArchSuffix) ==
|
|
llvm::ARM::ProfileKind::A) {
|
|
if (ArchName.find_lower("+nosha2") == StringRef::npos &&
|
|
CPUName.find_lower("+nosha2") == StringRef::npos)
|
|
Features.push_back("+sha2");
|
|
if (ArchName.find_lower("+noaes") == StringRef::npos &&
|
|
CPUName.find_lower("+noaes") == StringRef::npos)
|
|
Features.push_back("+aes");
|
|
} else {
|
|
D.Diag(clang::diag::warn_target_unsupported_extension)
|
|
<< "crypto"
|
|
<< llvm::ARM::getArchName(llvm::ARM::parseArch(ArchSuffix));
|
|
// With -fno-integrated-as -mfpu=crypto-neon-fp-armv8 some assemblers such as the GNU assembler
|
|
// will permit the use of crypto instructions as the fpu will override the architecture.
|
|
// We keep the crypto feature in this case to preserve compatibility.
|
|
// In all other cases we remove the crypto feature.
|
|
if (!Args.hasArg(options::OPT_fno_integrated_as))
|
|
Features.push_back("-crypto");
|
|
}
|
|
}
|
|
}
|
|
|
|
// CMSE: Check for target 8M (for -mcmse to be applicable) is performed later.
|
|
if (Args.getLastArg(options::OPT_mcmse))
|
|
Features.push_back("+8msecext");
|
|
|
|
// Look for the last occurrence of -mlong-calls or -mno-long-calls. If
|
|
// neither options are specified, see if we are compiling for kernel/kext and
|
|
// decide whether to pass "+long-calls" based on the OS and its version.
|
|
if (Arg *A = Args.getLastArg(options::OPT_mlong_calls,
|
|
options::OPT_mno_long_calls)) {
|
|
if (A->getOption().matches(options::OPT_mlong_calls))
|
|
Features.push_back("+long-calls");
|
|
} else if (KernelOrKext && (!Triple.isiOS() || Triple.isOSVersionLT(6)) &&
|
|
!Triple.isWatchOS()) {
|
|
Features.push_back("+long-calls");
|
|
}
|
|
|
|
// Generate execute-only output (no data access to code sections).
|
|
// This only makes sense for the compiler, not for the assembler.
|
|
if (!ForAS) {
|
|
// Supported only on ARMv6T2 and ARMv7 and above.
|
|
// Cannot be combined with -mno-movt or -mlong-calls
|
|
if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, options::OPT_mno_execute_only)) {
|
|
if (A->getOption().matches(options::OPT_mexecute_only)) {
|
|
if (getARMSubArchVersionNumber(Triple) < 7 &&
|
|
llvm::ARM::parseArch(Triple.getArchName()) != llvm::ARM::ArchKind::ARMV6T2)
|
|
D.Diag(diag::err_target_unsupported_execute_only) << Triple.getArchName();
|
|
else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
|
|
D.Diag(diag::err_opt_not_valid_with_opt) << A->getAsString(Args) << B->getAsString(Args);
|
|
// Long calls create constant pool entries and have not yet been fixed up
|
|
// to play nicely with execute-only. Hence, they cannot be used in
|
|
// execute-only code for now
|
|
else if (Arg *B = Args.getLastArg(options::OPT_mlong_calls, options::OPT_mno_long_calls)) {
|
|
if (B->getOption().matches(options::OPT_mlong_calls))
|
|
D.Diag(diag::err_opt_not_valid_with_opt) << A->getAsString(Args) << B->getAsString(Args);
|
|
}
|
|
Features.push_back("+execute-only");
|
|
}
|
|
}
|
|
}
|
|
|
|
// Kernel code has more strict alignment requirements.
|
|
if (KernelOrKext)
|
|
Features.push_back("+strict-align");
|
|
else if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
|
|
options::OPT_munaligned_access)) {
|
|
if (A->getOption().matches(options::OPT_munaligned_access)) {
|
|
// No v6M core supports unaligned memory access (v6M ARM ARM A3.2).
|
|
if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
|
|
D.Diag(diag::err_target_unsupported_unaligned) << "v6m";
|
|
// v8M Baseline follows on from v6M, so doesn't support unaligned memory
|
|
// access either.
|
|
else if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8m_baseline)
|
|
D.Diag(diag::err_target_unsupported_unaligned) << "v8m.base";
|
|
} else
|
|
Features.push_back("+strict-align");
|
|
} else {
|
|
// Assume pre-ARMv6 doesn't support unaligned accesses.
|
|
//
|
|
// ARMv6 may or may not support unaligned accesses depending on the
|
|
// SCTLR.U bit, which is architecture-specific. We assume ARMv6
|
|
// Darwin and NetBSD targets support unaligned accesses, and others don't.
|
|
//
|
|
// ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit
|
|
// which raises an alignment fault on unaligned accesses. Linux
|
|
// defaults this bit to 0 and handles it as a system-wide (not
|
|
// per-process) setting. It is therefore safe to assume that ARMv7+
|
|
// Linux targets support unaligned accesses. The same goes for NaCl.
|
|
//
|
|
// The above behavior is consistent with GCC.
|
|
int VersionNum = getARMSubArchVersionNumber(Triple);
|
|
if (Triple.isOSDarwin() || Triple.isOSNetBSD()) {
|
|
if (VersionNum < 6 ||
|
|
Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
|
|
Features.push_back("+strict-align");
|
|
} else if (Triple.isOSLinux() || Triple.isOSNaCl()) {
|
|
if (VersionNum < 7)
|
|
Features.push_back("+strict-align");
|
|
} else
|
|
Features.push_back("+strict-align");
|
|
}
|
|
|
|
// llvm does not support reserving registers in general. There is support
|
|
// for reserving r9 on ARM though (defined as a platform-specific register
|
|
// in ARM EABI).
|
|
if (Args.hasArg(options::OPT_ffixed_r9))
|
|
Features.push_back("+reserve-r9");
|
|
|
|
// The kext linker doesn't know how to deal with movw/movt.
|
|
if (KernelOrKext || Args.hasArg(options::OPT_mno_movt))
|
|
Features.push_back("+no-movt");
|
|
|
|
if (Args.hasArg(options::OPT_mno_neg_immediates))
|
|
Features.push_back("+no-neg-immediates");
|
|
|
|
// Enable/disable straight line speculation hardening.
|
|
if (Arg *A = Args.getLastArg(options::OPT_mharden_sls_EQ)) {
|
|
StringRef Scope = A->getValue();
|
|
bool EnableRetBr = false;
|
|
bool EnableBlr = false;
|
|
if (Scope != "none" && Scope != "all") {
|
|
SmallVector<StringRef, 4> Opts;
|
|
Scope.split(Opts, ",");
|
|
for (auto Opt : Opts) {
|
|
Opt = Opt.trim();
|
|
if (Opt == "retbr") {
|
|
EnableRetBr = true;
|
|
continue;
|
|
}
|
|
if (Opt == "blr") {
|
|
EnableBlr = true;
|
|
continue;
|
|
}
|
|
D.Diag(diag::err_invalid_sls_hardening)
|
|
<< Scope << A->getAsString(Args);
|
|
break;
|
|
}
|
|
} else if (Scope == "all") {
|
|
EnableRetBr = true;
|
|
EnableBlr = true;
|
|
}
|
|
|
|
if (EnableRetBr || EnableBlr)
|
|
if (!(isARMAProfile(Triple) && getARMSubArchVersionNumber(Triple) >= 7))
|
|
D.Diag(diag::err_sls_hardening_arm_not_supported)
|
|
<< Scope << A->getAsString(Args);
|
|
|
|
if (EnableRetBr)
|
|
Features.push_back("+harden-sls-retbr");
|
|
if (EnableBlr)
|
|
Features.push_back("+harden-sls-blr");
|
|
}
|
|
|
|
}
|
|
|
|
const std::string arm::getARMArch(StringRef Arch, const llvm::Triple &Triple) {
|
|
std::string MArch;
|
|
if (!Arch.empty())
|
|
MArch = std::string(Arch);
|
|
else
|
|
MArch = std::string(Triple.getArchName());
|
|
MArch = StringRef(MArch).split("+").first.lower();
|
|
|
|
// Handle -march=native.
|
|
if (MArch == "native") {
|
|
std::string CPU = std::string(llvm::sys::getHostCPUName());
|
|
if (CPU != "generic") {
|
|
// Translate the native cpu into the architecture suffix for that CPU.
|
|
StringRef Suffix = arm::getLLVMArchSuffixForARM(CPU, MArch, Triple);
|
|
// If there is no valid architecture suffix for this CPU we don't know how
|
|
// to handle it, so return no architecture.
|
|
if (Suffix.empty())
|
|
MArch = "";
|
|
else
|
|
MArch = std::string("arm") + Suffix.str();
|
|
}
|
|
}
|
|
|
|
return MArch;
|
|
}
|
|
|
|
/// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
|
|
StringRef arm::getARMCPUForMArch(StringRef Arch, const llvm::Triple &Triple) {
|
|
std::string MArch = getARMArch(Arch, Triple);
|
|
// getARMCPUForArch defaults to the triple if MArch is empty, but empty MArch
|
|
// here means an -march=native that we can't handle, so instead return no CPU.
|
|
if (MArch.empty())
|
|
return StringRef();
|
|
|
|
// We need to return an empty string here on invalid MArch values as the
|
|
// various places that call this function can't cope with a null result.
|
|
return Triple.getARMCPUForArch(MArch);
|
|
}
|
|
|
|
/// getARMTargetCPU - Get the (LLVM) name of the ARM cpu we are targeting.
|
|
std::string arm::getARMTargetCPU(StringRef CPU, StringRef Arch,
|
|
const llvm::Triple &Triple) {
|
|
// FIXME: Warn on inconsistent use of -mcpu and -march.
|
|
// If we have -mcpu=, use that.
|
|
if (!CPU.empty()) {
|
|
std::string MCPU = StringRef(CPU).split("+").first.lower();
|
|
// Handle -mcpu=native.
|
|
if (MCPU == "native")
|
|
return std::string(llvm::sys::getHostCPUName());
|
|
else
|
|
return MCPU;
|
|
}
|
|
|
|
return std::string(getARMCPUForMArch(Arch, Triple));
|
|
}
|
|
|
|
/// getLLVMArchSuffixForARM - Get the LLVM ArchKind value to use for a
|
|
/// particular CPU (or Arch, if CPU is generic). This is needed to
|
|
/// pass to functions like llvm::ARM::getDefaultFPU which need an
|
|
/// ArchKind as well as a CPU name.
|
|
llvm::ARM::ArchKind arm::getLLVMArchKindForARM(StringRef CPU, StringRef Arch,
|
|
const llvm::Triple &Triple) {
|
|
llvm::ARM::ArchKind ArchKind;
|
|
if (CPU == "generic" || CPU.empty()) {
|
|
std::string ARMArch = tools::arm::getARMArch(Arch, Triple);
|
|
ArchKind = llvm::ARM::parseArch(ARMArch);
|
|
if (ArchKind == llvm::ARM::ArchKind::INVALID)
|
|
// In case of generic Arch, i.e. "arm",
|
|
// extract arch from default cpu of the Triple
|
|
ArchKind = llvm::ARM::parseCPUArch(Triple.getARMCPUForArch(ARMArch));
|
|
} else {
|
|
// FIXME: horrible hack to get around the fact that Cortex-A7 is only an
|
|
// armv7k triple if it's actually been specified via "-arch armv7k".
|
|
ArchKind = (Arch == "armv7k" || Arch == "thumbv7k")
|
|
? llvm::ARM::ArchKind::ARMV7K
|
|
: llvm::ARM::parseCPUArch(CPU);
|
|
}
|
|
return ArchKind;
|
|
}
|
|
|
|
/// getLLVMArchSuffixForARM - Get the LLVM arch name to use for a particular
|
|
/// CPU (or Arch, if CPU is generic).
|
|
// FIXME: This is redundant with -mcpu, why does LLVM use this.
|
|
StringRef arm::getLLVMArchSuffixForARM(StringRef CPU, StringRef Arch,
|
|
const llvm::Triple &Triple) {
|
|
llvm::ARM::ArchKind ArchKind = getLLVMArchKindForARM(CPU, Arch, Triple);
|
|
if (ArchKind == llvm::ARM::ArchKind::INVALID)
|
|
return "";
|
|
return llvm::ARM::getSubArch(ArchKind);
|
|
}
|
|
|
|
void arm::appendBE8LinkFlag(const ArgList &Args, ArgStringList &CmdArgs,
|
|
const llvm::Triple &Triple) {
|
|
if (Args.hasArg(options::OPT_r))
|
|
return;
|
|
|
|
// ARMv7 (and later) and ARMv6-M do not support BE-32, so instruct the linker
|
|
// to generate BE-8 executables.
|
|
if (arm::getARMSubArchVersionNumber(Triple) >= 7 || arm::isARMMProfile(Triple))
|
|
CmdArgs.push_back("--be8");
|
|
}
|