179 lines
4.6 KiB
C++
179 lines
4.6 KiB
C++
//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features such as
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// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_TARGETPARSER_H
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#define LLVM_SUPPORT_TARGETPARSER_H
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// FIXME: vector is used because that's what clang uses for subtarget feature
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// lists, but SmallVector would probably be better
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/ARMTargetParser.h"
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#include "llvm/Support/AArch64TargetParser.h"
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#include <vector>
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namespace llvm {
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class StringRef;
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// Target specific information in their own namespaces.
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// (ARM/AArch64/X86 are declared in ARM/AArch64/X86TargetParser.h)
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// These should be generated from TableGen because the information is already
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// there, and there is where new information about targets will be added.
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// FIXME: To TableGen this we need to make some table generated files available
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// even if the back-end is not compiled with LLVM, plus we need to create a new
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// back-end to TableGen to create these clean tables.
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namespace AMDGPU {
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/// GPU kinds supported by the AMDGPU target.
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enum GPUKind : uint32_t {
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// Not specified processor.
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GK_NONE = 0,
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// R600-based processors.
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GK_R600 = 1,
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GK_R630 = 2,
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GK_RS880 = 3,
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GK_RV670 = 4,
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GK_RV710 = 5,
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GK_RV730 = 6,
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GK_RV770 = 7,
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GK_CEDAR = 8,
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GK_CYPRESS = 9,
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GK_JUNIPER = 10,
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GK_REDWOOD = 11,
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GK_SUMO = 12,
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GK_BARTS = 13,
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GK_CAICOS = 14,
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GK_CAYMAN = 15,
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GK_TURKS = 16,
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GK_R600_FIRST = GK_R600,
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GK_R600_LAST = GK_TURKS,
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// AMDGCN-based processors.
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GK_GFX600 = 32,
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GK_GFX601 = 33,
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GK_GFX602 = 34,
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GK_GFX700 = 40,
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GK_GFX701 = 41,
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GK_GFX702 = 42,
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GK_GFX703 = 43,
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GK_GFX704 = 44,
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GK_GFX705 = 45,
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GK_GFX801 = 50,
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GK_GFX802 = 51,
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GK_GFX803 = 52,
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GK_GFX805 = 53,
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GK_GFX810 = 54,
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GK_GFX900 = 60,
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GK_GFX902 = 61,
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GK_GFX904 = 62,
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GK_GFX906 = 63,
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GK_GFX908 = 64,
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GK_GFX909 = 65,
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GK_GFX90C = 66,
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GK_GFX1010 = 71,
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GK_GFX1011 = 72,
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GK_GFX1012 = 73,
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GK_GFX1030 = 75,
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GK_GFX1031 = 76,
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GK_GFX1032 = 77,
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GK_GFX1033 = 78,
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GK_AMDGCN_FIRST = GK_GFX600,
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GK_AMDGCN_LAST = GK_GFX1033,
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};
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/// Instruction set architecture version.
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struct IsaVersion {
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unsigned Major;
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unsigned Minor;
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unsigned Stepping;
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};
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// This isn't comprehensive for now, just things that are needed from the
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// frontend driver.
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enum ArchFeatureKind : uint32_t {
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FEATURE_NONE = 0,
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// These features only exist for r600, and are implied true for amdgcn.
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FEATURE_FMA = 1 << 1,
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FEATURE_LDEXP = 1 << 2,
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FEATURE_FP64 = 1 << 3,
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// Common features.
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FEATURE_FAST_FMA_F32 = 1 << 4,
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FEATURE_FAST_DENORMAL_F32 = 1 << 5,
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// Wavefront 32 is available.
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FEATURE_WAVE32 = 1 << 6,
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// Xnack is available.
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FEATURE_XNACK = 1 << 7,
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// Sram-ecc is available.
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FEATURE_SRAMECC = 1 << 8,
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};
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StringRef getArchNameAMDGCN(GPUKind AK);
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StringRef getArchNameR600(GPUKind AK);
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StringRef getCanonicalArchName(const Triple &T, StringRef Arch);
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GPUKind parseArchAMDGCN(StringRef CPU);
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GPUKind parseArchR600(StringRef CPU);
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unsigned getArchAttrAMDGCN(GPUKind AK);
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unsigned getArchAttrR600(GPUKind AK);
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void fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values);
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void fillValidArchListR600(SmallVectorImpl<StringRef> &Values);
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IsaVersion getIsaVersion(StringRef GPU);
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} // namespace AMDGPU
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namespace RISCV {
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enum CPUKind : unsigned {
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#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM,
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#include "RISCVTargetParser.def"
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};
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enum FeatureKind : unsigned {
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FK_INVALID = 0,
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FK_NONE = 1,
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FK_STDEXTM = 1 << 2,
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FK_STDEXTA = 1 << 3,
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FK_STDEXTF = 1 << 4,
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FK_STDEXTD = 1 << 5,
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FK_STDEXTC = 1 << 6,
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FK_64BIT = 1 << 7,
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};
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bool checkCPUKind(CPUKind Kind, bool IsRV64);
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bool checkTuneCPUKind(CPUKind Kind, bool IsRV64);
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CPUKind parseCPUKind(StringRef CPU);
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CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64);
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StringRef getMArchFromMcpu(StringRef CPU);
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
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void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
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bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector<StringRef> &Features);
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StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64);
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} // namespace RISCV
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} // namespace llvm
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#endif
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