// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s // --------------------------------------------------------------------------// // Immediate out of lower bound [-24, 21]. ld3h {z12.h, z13.h, z14.h}, p4/z, [x12, #-27, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21]. // CHECK-NEXT: ld3h {z12.h, z13.h, z14.h}, p4/z, [x12, #-27, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3h {z7.h, z8.h, z9.h}, p3/z, [x1, #24, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21]. // CHECK-NEXT: ld3h {z7.h, z8.h, z9.h}, p3/z, [x1, #24, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // --------------------------------------------------------------------------// // Immediate not a multiple of three. ld3h {z12.h, z13.h, z14.h}, p4/z, [x12, #-7, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21]. // CHECK-NEXT: ld3h {z12.h, z13.h, z14.h}, p4/z, [x12, #-7, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3h {z7.h, z8.h, z9.h}, p3/z, [x1, #5, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21]. // CHECK-NEXT: ld3h {z7.h, z8.h, z9.h}, p3/z, [x1, #5, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // --------------------------------------------------------------------------// // Invalid scalar + scalar addressing modes ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, xzr] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, xzr] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #2] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0, uxtw] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' // CHECK-NEXT: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // --------------------------------------------------------------------------// // error: invalid restricted predicate register, expected p0..p7 (without element suffix) ld3h {z2.h, z3.h, z4.h}, p8/z, [x15, #10, MUL VL] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) // CHECK-NEXT: ld3h {z2.h, z3.h, z4.h}, p8/z, [x15, #10, MUL VL] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // --------------------------------------------------------------------------// // Invalid vector list. ld3h { }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected // CHECK-NEXT: ld3h { }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld3h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3h { z0.h, z1.h, z2.s }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix // CHECK-NEXT: ld3h { z0.h, z1.h, z2.s }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3h { z0.h, z1.h, z3.h }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential // CHECK-NEXT: ld3h { z0.h, z1.h, z3.h }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK-NEXT: ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // --------------------------------------------------------------------------// // Negative tests for instructions that are incompatible with movprfx movprfx z21.h, p5/z, z28.h ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov // CHECK-NEXT: ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: movprfx z21, z28 ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov // CHECK-NEXT: ld3h { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: