; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; NOTE: Assertions have been autoenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK

define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){
; CHECK-LABEL: ctpop_2i64_t:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    .save {r4, lr}
; CHECK-NEXT:    push {r4, lr}
; CHECK-NEXT:    vmov r0, s3
; CHECK-NEXT:    mov.w r1, #1431655765
; CHECK-NEXT:    mov.w lr, #858993459
; CHECK-NEXT:    mov.w r4, #16843009
; CHECK-NEXT:    and.w r2, r1, r0, lsr #1
; CHECK-NEXT:    subs r0, r0, r2
; CHECK-NEXT:    and.w r3, lr, r0, lsr #2
; CHECK-NEXT:    bic r0, r0, #-858993460
; CHECK-NEXT:    add r0, r3
; CHECK-NEXT:    vmov r3, s2
; CHECK-NEXT:    add.w r0, r0, r0, lsr #4
; CHECK-NEXT:    bic r12, r0, #-252645136
; CHECK-NEXT:    and.w r0, r1, r3, lsr #1
; CHECK-NEXT:    subs r0, r3, r0
; CHECK-NEXT:    and.w r3, lr, r0, lsr #2
; CHECK-NEXT:    bic r0, r0, #-858993460
; CHECK-NEXT:    add r0, r3
; CHECK-NEXT:    vmov r3, s0
; CHECK-NEXT:    add.w r0, r0, r0, lsr #4
; CHECK-NEXT:    bic r0, r0, #-252645136
; CHECK-NEXT:    muls r0, r4, r0
; CHECK-NEXT:    lsrs r0, r0, #24
; CHECK-NEXT:    and.w r2, r1, r3, lsr #1
; CHECK-NEXT:    subs r2, r3, r2
; CHECK-NEXT:    and.w r3, lr, r2, lsr #2
; CHECK-NEXT:    bic r2, r2, #-858993460
; CHECK-NEXT:    add r2, r3
; CHECK-NEXT:    vmov r3, s1
; CHECK-NEXT:    vldr s1, .LCPI0_0
; CHECK-NEXT:    add.w r2, r2, r2, lsr #4
; CHECK-NEXT:    bic r2, r2, #-252645136
; CHECK-NEXT:    muls r2, r4, r2
; CHECK-NEXT:    lsrs r2, r2, #24
; CHECK-NEXT:    and.w r1, r1, r3, lsr #1
; CHECK-NEXT:    subs r1, r3, r1
; CHECK-NEXT:    and.w r3, lr, r1, lsr #2
; CHECK-NEXT:    bic r1, r1, #-858993460
; CHECK-NEXT:    add r1, r3
; CHECK-NEXT:    mul r3, r12, r4
; CHECK-NEXT:    add.w r1, r1, r1, lsr #4
; CHECK-NEXT:    bic r1, r1, #-252645136
; CHECK-NEXT:    muls r1, r4, r1
; CHECK-NEXT:    add.w r0, r0, r3, lsr #24
; CHECK-NEXT:    vmov s2, r0
; CHECK-NEXT:    add.w r0, r2, r1, lsr #24
; CHECK-NEXT:    vmov s0, r0
; CHECK-NEXT:    vmov.f32 s3, s1
; CHECK-NEXT:    pop {r4, pc}
; CHECK-NEXT:    .p2align 2
; CHECK-NEXT:  @ %bb.1:
; CHECK-NEXT:  .LCPI0_0:
; CHECK-NEXT:    .long 0x00000000 @ float 0
entry:
  %0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src)
  ret <2 x i64> %0
}

define arm_aapcs_vfpcc <4 x i32> @ctpop_4i32_t(<4 x i32> %src){
; CHECK-LABEL: ctpop_4i32_t:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
; CHECK-NEXT:    vpush {d8, d9, d10, d11}
; CHECK-NEXT:    vmov.i8 q4, #0x55
; CHECK-NEXT:    vshr.u32 q5, q0, #1
; CHECK-NEXT:    vand q4, q5, q4
; CHECK-NEXT:    vmov.i8 q3, #0x33
; CHECK-NEXT:    vsub.i32 q0, q0, q4
; CHECK-NEXT:    vmov.i8 q2, #0xf
; CHECK-NEXT:    vshr.u32 q4, q0, #2
; CHECK-NEXT:    vand q0, q0, q3
; CHECK-NEXT:    vand q4, q4, q3
; CHECK-NEXT:    vmov.i8 q1, #0x1
; CHECK-NEXT:    vadd.i32 q0, q0, q4
; CHECK-NEXT:    vshr.u32 q3, q0, #4
; CHECK-NEXT:    vadd.i32 q0, q0, q3
; CHECK-NEXT:    vand q0, q0, q2
; CHECK-NEXT:    vmul.i32 q0, q0, q1
; CHECK-NEXT:    vshr.u32 q0, q0, #24
; CHECK-NEXT:    vpop {d8, d9, d10, d11}
; CHECK-NEXT:    bx lr
entry:
  %0 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %src)
  ret <4 x i32> %0
}

define arm_aapcs_vfpcc <8 x i16> @ctpop_8i16_t(<8 x i16> %src){
; CHECK-LABEL: ctpop_8i16_t:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    .vsave {d8, d9, d10, d11}
; CHECK-NEXT:    vpush {d8, d9, d10, d11}
; CHECK-NEXT:    vmov.i8 q4, #0x55
; CHECK-NEXT:    vshr.u16 q5, q0, #1
; CHECK-NEXT:    vand q4, q5, q4
; CHECK-NEXT:    vmov.i8 q3, #0x33
; CHECK-NEXT:    vsub.i16 q0, q0, q4
; CHECK-NEXT:    vmov.i8 q2, #0xf
; CHECK-NEXT:    vshr.u16 q4, q0, #2
; CHECK-NEXT:    vand q0, q0, q3
; CHECK-NEXT:    vand q4, q4, q3
; CHECK-NEXT:    vmov.i8 q1, #0x1
; CHECK-NEXT:    vadd.i16 q0, q0, q4
; CHECK-NEXT:    vshr.u16 q3, q0, #4
; CHECK-NEXT:    vadd.i16 q0, q0, q3
; CHECK-NEXT:    vand q0, q0, q2
; CHECK-NEXT:    vmul.i16 q0, q0, q1
; CHECK-NEXT:    vshr.u16 q0, q0, #8
; CHECK-NEXT:    vpop {d8, d9, d10, d11}
; CHECK-NEXT:    bx lr
entry:
  %0 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %src)
  ret <8 x i16> %0
}

define arm_aapcs_vfpcc <16 x i8> @ctpop_16i8_t(<16 x i8> %src){
; CHECK-LABEL: ctpop_16i8_t:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    .vsave {d8, d9}
; CHECK-NEXT:    vpush {d8, d9}
; CHECK-NEXT:    vmov.i8 q3, #0x55
; CHECK-NEXT:    vshr.u8 q4, q0, #1
; CHECK-NEXT:    vand q3, q4, q3
; CHECK-NEXT:    vmov.i8 q2, #0x33
; CHECK-NEXT:    vsub.i8 q0, q0, q3
; CHECK-NEXT:    vmov.i8 q1, #0xf
; CHECK-NEXT:    vshr.u8 q3, q0, #2
; CHECK-NEXT:    vand q0, q0, q2
; CHECK-NEXT:    vand q3, q3, q2
; CHECK-NEXT:    vadd.i8 q0, q0, q3
; CHECK-NEXT:    vshr.u8 q2, q0, #4
; CHECK-NEXT:    vadd.i8 q0, q0, q2
; CHECK-NEXT:    vand q0, q0, q1
; CHECK-NEXT:    vpop {d8, d9}
; CHECK-NEXT:    bx lr
entry:
  %0 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %src)
  ret <16 x i8> %0
}

declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>)
declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>)
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>)