; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s define @vsplat_nxv1i1_0() { ; CHECK-LABEL: vsplat_nxv1i1_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer ret %splat } define @vsplat_nxv1i1_1() { ; CHECK-LABEL: vsplat_nxv1i1_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer ret %splat } define @vsplat_nxv2i1_0() { ; CHECK-LABEL: vsplat_nxv2i1_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer ret %splat } define @vsplat_nxv2i1_1() { ; CHECK-LABEL: vsplat_nxv2i1_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer ret %splat } define @vsplat_nxv4i1_0() { ; CHECK-LABEL: vsplat_nxv4i1_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer ret %splat } define @vsplat_nxv4i1_1() { ; CHECK-LABEL: vsplat_nxv4i1_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer ret %splat } define @vsplat_nxv8i1_0() { ; CHECK-LABEL: vsplat_nxv8i1_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer ret %splat } define @vsplat_nxv8i1_1() { ; CHECK-LABEL: vsplat_nxv8i1_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer ret %splat } define @vsplat_nxv16i1_0() { ; CHECK-LABEL: vsplat_nxv16i1_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer ret %splat } define @vsplat_nxv16i1_1() { ; CHECK-LABEL: vsplat_nxv16i1_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret %head = insertelement undef, i1 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer ret %splat }