# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -amdgpu-global-isel-new-legality -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s

--- |
  define amdgpu_kernel void @load_global_v8i32_non_uniform(<8 x i32> addrspace(1)* %in) {
    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
    %global.not.uniform.v8i32 = getelementptr <8 x i32>, <8 x i32> addrspace(1)* %in, i32 %tmp0
    %tmp2 = load <8 x i32>, <8 x i32> addrspace(1)* %global.not.uniform.v8i32
    ret void
  }

  define amdgpu_kernel void @load_global_v4i64_non_uniform(<4 x i64> addrspace(1)* %in) {
    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
    %global.not.uniform.v4i64 = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i32 %tmp0
    %tmp2 = load <4 x i64>, <4 x i64> addrspace(1)* %global.not.uniform.v4i64
    ret void
  }
  define amdgpu_kernel void @load_global_v16i32_non_uniform(<16 x i32> addrspace(1)* %in) {
    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
    %global.not.uniform.v16i32 = getelementptr <16 x i32>, <16 x i32> addrspace(1)* %in, i32 %tmp0
    %tmp2 = load <16 x i32>, <16 x i32> addrspace(1)* %global.not.uniform.v16i32
    ret void
  }
  define amdgpu_kernel void @load_global_v8i64_non_uniform(<8 x i64> addrspace(1)* %in) {
    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
    %global.not.uniform.v8i64 = getelementptr <8 x i64>, <8 x i64> addrspace(1)* %in, i32 %tmp0
    %tmp2 = load <8 x i64>, <8 x i64> addrspace(1)* %global.not.uniform.v8i64
    ret void
  }
  define amdgpu_kernel void @load_global_v8i32_uniform() {ret void}
  define amdgpu_kernel void @load_global_v4i64_uniform() {ret void}
  define amdgpu_kernel void @load_global_v16i32_uniform() {ret void}
  define amdgpu_kernel void @load_global_v8i64_uniform() {ret void}
  define amdgpu_kernel void @load_constant_v8i32_non_uniform(<8 x i32> addrspace(4)* %in) {
    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
    %constant.not.uniform.v8i32 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %in, i32 %tmp0
    %tmp2 = load <8 x i32>, <8 x i32> addrspace(4)* %constant.not.uniform.v8i32
    ret void
  }

  define amdgpu_kernel void @load_constant_i256_non_uniform(i256 addrspace(4)* %in) {
    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
    %constant.not.uniform = getelementptr i256, i256 addrspace(4)* %in, i32 %tmp0
    %tmp2 = load i256, i256 addrspace(4)* %constant.not.uniform
    ret void
  }

  define amdgpu_kernel void @load_constant_v16i16_non_uniform(<16 x i16> addrspace(4)* %in) {
    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
    %constant.not.uniform = getelementptr <16 x i16>, <16 x i16> addrspace(4)* %in, i32 %tmp0
    %tmp2 = load <16 x i16>, <16 x i16> addrspace(4)* %constant.not.uniform
    ret void
  }

  define amdgpu_kernel void @load_constant_v4i64_non_uniform(<4 x i64> addrspace(4)* %in) {
    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
    %constant.not.uniform.v4i64 = getelementptr <4 x i64>, <4 x i64> addrspace(4)* %in, i32 %tmp0
    %tmp2 = load <4 x i64>, <4 x i64> addrspace(4)* %constant.not.uniform.v4i64
    ret void
  }
  define amdgpu_kernel void @load_constant_v16i32_non_uniform(<16 x i32> addrspace(4)* %in) {
    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
    %constant.not.uniform.v16i32 = getelementptr <16 x i32>, <16 x i32> addrspace(4)* %in, i32 %tmp0
    %tmp2 = load <16 x i32>, <16 x i32> addrspace(4)* %constant.not.uniform.v16i32
    ret void
  }
  define amdgpu_kernel void @load_constant_v8i64_non_uniform(<8 x i64> addrspace(4)* %in) {
    %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
    %constant.not.uniform.v8i64 = getelementptr <8 x i64>, <8 x i64> addrspace(4)* %in, i32 %tmp0
    %tmp2 = load <8 x i64>, <8 x i64> addrspace(4)* %constant.not.uniform.v8i64
    ret void
  }

  define amdgpu_kernel void @load_constant_v8i32_uniform() {ret void}
  define amdgpu_kernel void @load_constant_v16i16_uniform() {ret void}
  define amdgpu_kernel void @load_constant_v4i64_uniform() {ret void}
  define amdgpu_kernel void @load_constant_v16i32_uniform() {ret void}
  define amdgpu_kernel void @load_constant_v8i64_uniform() {ret void}
  define amdgpu_kernel void @load_local_uniform() { ret void }
  define amdgpu_kernel void @load_region_uniform() { ret void }
  define amdgpu_kernel void @extload_constant_i8_to_i32_uniform() { ret void }
  define amdgpu_kernel void @extload_global_i8_to_i32_uniform() { ret void }
  define amdgpu_kernel void @extload_constant_i16_to_i32_uniform() { ret void }
  define amdgpu_kernel void @extload_global_i16_to_i32_uniform() { ret void }
  define amdgpu_kernel void @load_constant_i32_uniform_align4() {ret void}
  define amdgpu_kernel void @load_constant_i32_uniform_align2() {ret void}
  define amdgpu_kernel void @load_constant_i32_uniform_align1() {ret void}
  define amdgpu_kernel void @load_private_uniform_sgpr_i32() {ret void}
  define amdgpu_kernel void @load_constant_v8i32_vgpr_crash() { ret void }
  define amdgpu_kernel void @load_constant_v8i32_vgpr_crash_loop_phi() { ret void }

  define amdgpu_kernel void @load_constant_v3i32_align4() { ret void }
  define amdgpu_kernel void @load_constant_v3i32_align8() { ret void }
  define amdgpu_kernel void @load_constant_v3i32_align16() { ret void }

  define amdgpu_kernel void @load_constant_v6i16_align4() { ret void }
  define amdgpu_kernel void @load_constant_v6i16_align8() { ret void }
  define amdgpu_kernel void @load_constant_v6i16_align16() { ret void }

  define amdgpu_kernel void @load_constant_i96_align4() { ret void }
  define amdgpu_kernel void @load_constant_i96_align8() { ret void }
  define amdgpu_kernel void @load_constant_i96_align16() { ret void }

  declare i32 @llvm.amdgcn.workitem.id.x() #0
  attributes #0 = { nounwind readnone }
...

---
name: load_global_v8i32_non_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_global_v8i32_non_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load 16 from %ir.global.not.uniform.v8i32, align 32, addrspace 1)
    ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
    ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p1) :: (load 16 from %ir.global.not.uniform.v8i32 + 16, basealign 32, addrspace 1)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(<8 x s32>) = G_LOAD %0 :: (load 32 from %ir.global.not.uniform.v8i32)
...

---
name: load_global_v4i64_non_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: load_global_v4i64_non_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[COPY]](p1) :: (load 16 from %ir.global.not.uniform.v4i64, align 32, addrspace 1)
    ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
    ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD]](p1) :: (load 16 from %ir.global.not.uniform.v4i64 + 16, basealign 32, addrspace 1)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(<4 x s64>) = G_LOAD %0 :: (load 32 from %ir.global.not.uniform.v4i64)
...

---
name: load_global_v16i32_non_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_global_v16i32_non_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p1) = COPY [[COPY]](p1)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[COPY]](p1) :: (load 16 from %ir.global.not.uniform.v16i32, align 64, addrspace 1)
    ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
    ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p1) :: (load 16 from %ir.global.not.uniform.v16i32 + 16, basealign 64, addrspace 1)
    ; CHECK: [[C1:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 32
    ; CHECK: [[PTR_ADD1:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
    ; CHECK: [[LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD1]](p1) :: (load 16 from %ir.global.not.uniform.v16i32 + 32, align 32, basealign 64, addrspace 1)
    ; CHECK: [[C2:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 48
    ; CHECK: [[PTR_ADD2:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
    ; CHECK: [[LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD2]](p1) :: (load 16 from %ir.global.not.uniform.v16i32 + 48, basealign 64, addrspace 1)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>), [[LOAD2]](<4 x s32>), [[LOAD3]](<4 x s32>)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(<16 x s32>) = G_LOAD %0 :: (load 64 from %ir.global.not.uniform.v16i32)
...

name: load_global_v8i64_non_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_global_v8i64_non_uniform
    ; CHECK: [[PTR:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD0:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR]](p1) :: (load 16 from %ir.global.not.uniform.v8i64, align 64, addrspace 1)
    ; CHECK: [[OFFSET16:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
    ; CHECK: [[GEP16:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[PTR]], [[OFFSET16]](s64)
    ; CHECK: [[LOAD16:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[GEP16]](p1) :: (load 16 from %ir.global.not.uniform.v8i64 + 16, basealign 64, addrspace 1)
    ; CHECK: [[OFFSET32:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 32
    ; CHECK: [[GEP32:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[PTR]], [[OFFSET32]](s64)
    ; CHECK: [[LOAD32:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[GEP32]](p1) :: (load 16 from %ir.global.not.uniform.v8i64 + 32, align 32, basealign 64, addrspace 1)
    ; CHECK: [[OFFSET48:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 48
    ; CHECK: [[GEP48:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[PTR]], [[OFFSET48]](s64)
    ; CHECK: [[LOAD48:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[GEP48]](p1) :: (load 16 from %ir.global.not.uniform.v8i64 + 48, basealign 64, addrspace 1)
    ; CHECK: %1:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[LOAD0]](<2 x s64>), [[LOAD16]](<2 x s64>), [[LOAD32]](<2 x s64>), [[LOAD48]](<2 x s64>)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(<8 x s64>) = G_LOAD %0 :: (load 64 from %ir.global.not.uniform.v8i64)
...

---
name: load_global_v8i32_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_global_v8i32_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<8 x s32>) = G_LOAD [[COPY]](p1) :: (invariant load 32, addrspace 1)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(<8 x s32>) = G_LOAD %0 :: (invariant load 32, addrspace 1)
...

---
name: load_global_v4i64_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_global_v4i64_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<4 x s64>) = G_LOAD [[COPY]](p1) :: (invariant load 32, addrspace 1)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(<4 x s64>) = G_LOAD %0 :: (invariant load 32, addrspace 1)
...

---
name: load_global_v16i32_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_global_v16i32_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<16 x s32>) = G_LOAD [[COPY]](p1) :: (invariant load 64, addrspace 1)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(<16 x s32>) = G_LOAD %0 :: (invariant load 64, addrspace 1)
...

---
name: load_global_v8i64_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_global_v8i64_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<8 x s64>) = G_LOAD [[COPY]](p1) :: (invariant load 64, addrspace 1)
    %0:_(p1) = COPY $sgpr0_sgpr1
    %1:_(<8 x s64>) = G_LOAD %0 :: (invariant load 64, addrspace 1)
...

---
name: load_constant_v8i32_non_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v8i32_non_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform.v8i32, align 32, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
    ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform.v8i32 + 16, basealign 32, addrspace 4)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<8 x s32>) = G_LOAD %0 :: (load 32 from %ir.constant.not.uniform.v8i32)
...

---
name: load_constant_i256_non_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_i256_non_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s128) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform, align 32, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
    ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(s128) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform + 16, basealign 32, addrspace 4)
    ; CHECK: [[MV:%[0-9]+]]:vgpr(s256) = G_MERGE_VALUES [[LOAD]](s128), [[LOAD1]](s128)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(s256) = G_LOAD %0 :: (load 32 from %ir.constant.not.uniform)
...

---
name: load_constant_v16i16_non_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: load_constant_v16i16_non_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<8 x s16>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform, align 32, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
    ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<8 x s16>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform + 16, basealign 32, addrspace 4)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s16>) = G_CONCAT_VECTORS [[LOAD]](<8 x s16>), [[LOAD1]](<8 x s16>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<16 x s16>) = G_LOAD %0 :: (load 32 from %ir.constant.not.uniform)
...

---
name: load_constant_v4i64_non_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v4i64_non_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform.v4i64, align 32, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
    ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform.v4i64 + 16, basealign 32, addrspace 4)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<4 x s64>) = G_LOAD %0 :: (load 32 from %ir.constant.not.uniform.v4i64)
...

---
name: load_constant_v16i32_non_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v16i32_non_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform.v16i32, align 64, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
    ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform.v16i32 + 16, basealign 64, addrspace 4)
    ; CHECK: [[C1:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 32
    ; CHECK: [[PTR_ADD1:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
    ; CHECK: [[LOAD2:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD1]](p4) :: (load 16 from %ir.constant.not.uniform.v16i32 + 32, align 32, basealign 64, addrspace 4)
    ; CHECK: [[C2:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 48
    ; CHECK: [[PTR_ADD2:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
    ; CHECK: [[LOAD3:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD2]](p4) :: (load 16 from %ir.constant.not.uniform.v16i32 + 48, basealign 64, addrspace 4)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<16 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>), [[LOAD2]](<4 x s32>), [[LOAD3]](<4 x s32>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<16 x s32>) = G_LOAD %0 :: (load 64 from %ir.constant.not.uniform.v16i32)
...

---
name: load_constant_v8i64_non_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v8i64_non_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform.v8i64, align 64, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
    ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 from %ir.constant.not.uniform.v8i64 + 16, basealign 64, addrspace 4)
    ; CHECK: [[C1:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 32
    ; CHECK: [[PTR_ADD1:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C1]](s64)
    ; CHECK: [[LOAD2:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD1]](p4) :: (load 16 from %ir.constant.not.uniform.v8i64 + 32, align 32, basealign 64, addrspace 4)
    ; CHECK: [[C2:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 48
    ; CHECK: [[PTR_ADD2:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
    ; CHECK: [[LOAD3:%[0-9]+]]:vgpr(<2 x s64>) = G_LOAD [[PTR_ADD2]](p4) :: (load 16 from %ir.constant.not.uniform.v8i64 + 48, basealign 64, addrspace 4)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s64>) = G_CONCAT_VECTORS [[LOAD]](<2 x s64>), [[LOAD1]](<2 x s64>), [[LOAD2]](<2 x s64>), [[LOAD3]](<2 x s64>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<8 x s64>) = G_LOAD %0 :: (load 64 from %ir.constant.not.uniform.v8i64)
...

---
name: load_constant_v8i32_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v8i32_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<8 x s32>) = G_LOAD [[COPY]](p4) :: (load 32, addrspace 4)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<8 x s32>) = G_LOAD %0 :: (load 32, addrspace 4)
...

---
name: load_constant_v16i16_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v16i16_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<16 x s16>) = G_LOAD [[COPY]](p4) :: (load 32, addrspace 4)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<16 x s16>) = G_LOAD %0 :: (load 32, addrspace 4)
...

---
name: load_constant_v4i64_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v4i64_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<4 x s64>) = G_LOAD [[COPY]](p4) :: (load 32, addrspace 4)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<4 x s64>) = G_LOAD %0 :: (load 32, addrspace 4)
...

---
name: load_constant_v16i32_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v16i32_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<16 x s32>) = G_LOAD [[COPY]](p4) :: (load 64, addrspace 4)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<16 x s32>) = G_LOAD %0 :: (load 64, addrspace 4)
...

---
name: load_constant_v8i64_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v8i64_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<8 x s64>) = G_LOAD [[COPY]](p4) :: (load 64, addrspace 4)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<8 x s64>) = G_LOAD %0 :: (load 64, addrspace 4)
...

---
name: load_local_uniform
legalized: true
body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: load_local_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p3) :: (load 4, addrspace 3)
    %0:_(p3) = COPY $sgpr0
    %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 3)

...
---
name: load_region_uniform
legalized: true
body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: load_region_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p3) :: (load 4, addrspace 5)
    %0:_(p3) = COPY $sgpr0
    %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 5)

...

---
name: extload_constant_i8_to_i32_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: extload_constant_i8_to_i32_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 1, addrspace 4)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(s32) = G_LOAD %0 :: (load 1, addrspace 4, align 1)
...

---
name: extload_global_i8_to_i32_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: extload_global_i8_to_i32_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 1, addrspace 1)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(s32) = G_LOAD %0 :: (load 1, addrspace 1, align 1)
...

---
name: extload_constant_i16_to_i32_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: extload_constant_i16_to_i32_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 2, addrspace 4)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(s32) = G_LOAD %0 :: (load 2, addrspace 4, align 2)
...

---
name: extload_global_i16_to_i32_uniform
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: extload_global_i16_to_i32_uniform
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 2, addrspace 1)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(s32) = G_LOAD %0 :: (load 2, addrspace 1, align 2)
...

---
name: load_constant_i32_uniform_align4
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_i32_uniform_align4
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(s32) = G_LOAD [[COPY]](p4) :: (load 4, addrspace 4)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 4, align 4)
...

---
name: load_constant_i32_uniform_align2
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: load_constant_i32_uniform_align2
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 4, align 2, addrspace 4)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 4, align 2)
...

---
name: load_constant_i32_uniform_align1
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: load_constant_i32_uniform_align1
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p4) = COPY [[COPY]](p4)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p4) :: (load 4, align 1, addrspace 4)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 4, align 1)
...

---
name: load_private_uniform_sgpr_i32
legalized: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: load_private_uniform_sgpr_i32
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(p5) = COPY [[COPY]](p5)
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY1]](p5) :: (load 4, addrspace 5)
    %0:_(p5) = COPY $sgpr0
    %1:_(s32) = G_LOAD %0 :: (load 4, addrspace 5, align 4)
...

---
name: load_constant_v8i32_vgpr_crash
legalized: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: load_constant_v8i32_vgpr_crash
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(p4) = COPY $vgpr0_vgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[COPY]](p4) :: (load 16, align 32, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
    ; CHECK: [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 + 16, addrspace 4)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>)
    %0:_(p4) = COPY $vgpr0_vgpr1
    %1:_(<8 x s32>) = G_LOAD %0 :: (load 32, addrspace 4)
...

---
name: load_constant_v8i32_vgpr_crash_loop_phi
legalized: true
tracksRegLiveness: true

body: |
  ; CHECK-LABEL: name: load_constant_v8i32_vgpr_crash_loop_phi
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
  ; CHECK:   [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
  ; CHECK:   [[COPY1:%[0-9]+]]:sgpr(p4) = COPY $sgpr2_sgpr3
  ; CHECK:   G_BR %bb.1
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   [[PHI:%[0-9]+]]:vgpr(p4) = G_PHI [[COPY]](p4), %bb.0, %3(p4), %bb.1
  ; CHECK:   [[LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PHI]](p4) :: (load 16, align 32, addrspace 4)
  ; CHECK:   [[C:%[0-9]+]]:vgpr(s64) = G_CONSTANT i64 16
  ; CHECK:   [[PTR_ADD:%[0-9]+]]:vgpr(p4) = G_PTR_ADD [[PHI]], [[C]](s64)
  ; CHECK:   [[LOAD1:%[0-9]+]]:vgpr(<4 x s32>) = G_LOAD [[PTR_ADD]](p4) :: (load 16 + 16, addrspace 4)
  ; CHECK:   [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<8 x s32>) = G_CONCAT_VECTORS [[LOAD]](<4 x s32>), [[LOAD1]](<4 x s32>)
  ; CHECK:   [[COPY2:%[0-9]+]]:sgpr(p4) = COPY [[COPY1]](p4)
  ; CHECK:   G_BR %bb.1
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3


    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(p4) = COPY $sgpr2_sgpr3
    G_BR %bb.1

  bb.1:
    %2:_(p4) = G_PHI %0, %bb.0, %4, %bb.1
    %3:_(<8 x s32>) = G_LOAD %2 :: (load 32, addrspace 4)
    %4:_(p4) = COPY %1
    G_BR %bb.1
...

---
name: load_constant_v3i32_align4
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v3i32_align4
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (invariant load 8, align 4, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
    ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, addrspace 4)
    ; CHECK: [[DEF:%[0-9]+]]:sgpr(<3 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
    ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
    ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](<3 x s32>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<3 x s32>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 4)
    S_ENDPGM 0, implicit %1
...

---
name: load_constant_v3i32_align8
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v3i32_align8
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (invariant load 8, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
    ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, align 8, addrspace 4)
    ; CHECK: [[DEF:%[0-9]+]]:sgpr(<3 x s32>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
    ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
    ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](<3 x s32>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<3 x s32>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 8)
    S_ENDPGM 0, implicit %1
...

---
name: load_constant_v3i32_align16
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v3i32_align16
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<4 x s32>) = G_LOAD [[COPY]](p4) :: (invariant load 16, addrspace 4)
    ; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(<3 x s32>) = G_EXTRACT [[LOAD]](<4 x s32>), 0
    ; CHECK: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s32>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<3 x s32>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 16)
    S_ENDPGM 0, implicit %1
...

---
name: load_constant_v6i16_align4
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v6i16_align4
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<4 x s16>) = G_LOAD [[COPY]](p4) :: (invariant load 8, align 4, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
    ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(<2 x s16>) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, addrspace 4)
    ; CHECK: [[DEF:%[0-9]+]]:sgpr(<6 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT:%[0-9]+]]:sgpr(<6 x s16>) = G_INSERT [[DEF]], [[LOAD]](<4 x s16>), 0
    ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(<6 x s16>) = G_INSERT [[INSERT]], [[LOAD1]](<2 x s16>), 64
    ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](<6 x s16>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<6 x s16>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 4)
    S_ENDPGM 0, implicit %1
...

---
name: load_constant_v6i16_align8
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v6i16_align8
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<4 x s16>) = G_LOAD [[COPY]](p4) :: (invariant load 8, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
    ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(<2 x s16>) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, align 8, addrspace 4)
    ; CHECK: [[DEF:%[0-9]+]]:sgpr(<6 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT:%[0-9]+]]:sgpr(<6 x s16>) = G_INSERT [[DEF]], [[LOAD]](<4 x s16>), 0
    ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(<6 x s16>) = G_INSERT [[INSERT]], [[LOAD1]](<2 x s16>), 64
    ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](<6 x s16>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<6 x s16>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 8)
    S_ENDPGM 0, implicit %1
...

---
name: load_constant_v6i16_align16
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_v6i16_align16
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(<8 x s16>) = G_LOAD [[COPY]](p4) :: (invariant load 16, addrspace 4)
    ; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(<6 x s16>) = G_EXTRACT [[LOAD]](<8 x s16>), 0
    ; CHECK: S_ENDPGM 0, implicit [[EXTRACT]](<6 x s16>)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(<6 x s16>) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 16)
    S_ENDPGM 0, implicit %1
...

---
name: load_constant_i96_align4
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_i96_align4
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(s64) = G_LOAD [[COPY]](p4) :: (invariant load 8, align 4, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
    ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, addrspace 4)
    ; CHECK: [[DEF:%[0-9]+]]:sgpr(s96) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT:%[0-9]+]]:sgpr(s96) = G_INSERT [[DEF]], [[LOAD]](s64), 0
    ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(s96) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
    ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](s96)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(s96) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 4)
    S_ENDPGM 0, implicit %1
...

---
name: load_constant_i96_align8
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_i96_align8
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(s64) = G_LOAD [[COPY]](p4) :: (invariant load 8, addrspace 4)
    ; CHECK: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
    ; CHECK: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
    ; CHECK: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (invariant load 4 + 8, align 8, addrspace 4)
    ; CHECK: [[DEF:%[0-9]+]]:sgpr(s96) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT:%[0-9]+]]:sgpr(s96) = G_INSERT [[DEF]], [[LOAD]](s64), 0
    ; CHECK: [[INSERT1:%[0-9]+]]:sgpr(s96) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
    ; CHECK: S_ENDPGM 0, implicit [[INSERT1]](s96)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(s96) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 8)
    S_ENDPGM 0, implicit %1
...

---
name: load_constant_i96_align16
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: load_constant_i96_align16
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
    ; CHECK: [[LOAD:%[0-9]+]]:sgpr(s128) = G_LOAD [[COPY]](p4) :: (invariant load 16, addrspace 4)
    ; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(s96) = G_EXTRACT [[LOAD]](s128), 0
    ; CHECK: S_ENDPGM 0, implicit [[EXTRACT]](s96)
    %0:_(p4) = COPY $sgpr0_sgpr1
    %1:_(s96) = G_LOAD %0 :: (invariant load 12, addrspace 4, align 16)
    S_ENDPGM 0, implicit %1
...