# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck %s --- name: fceil_s32_vv legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $vgpr0 ; CHECK-LABEL: name: fceil_s32_vv ; CHECK: liveins: $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: %1:vgpr_32 = nofpexcept V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: $vgpr0 = COPY %1 %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = G_FCEIL %0 $vgpr0 = COPY %1 ... --- name: fceil_s32_vs legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $sgpr0 ; CHECK-LABEL: name: fceil_s32_vs ; CHECK: liveins: $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: %1:vgpr_32 = nofpexcept V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: $vgpr0 = COPY %1 %0:sgpr(s32) = COPY $sgpr0 %1:vgpr(s32) = G_FCEIL %0 $vgpr0 = COPY %1 ... --- name: fceil_s64_sv legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $sgpr0_sgpr1 ; CHECK-LABEL: name: fceil_s64_sv ; CHECK: liveins: $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: %1:vreg_64 = nofpexcept V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: $vgpr0_vgpr1 = COPY %1 %0:sgpr(s64) = COPY $sgpr0_sgpr1 %1:vgpr(s64) = G_FCEIL %0 $vgpr0_vgpr1 = COPY %1 ... --- name: fceil_s64_vv legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $vgpr0_vgpr1 ; CHECK-LABEL: name: fceil_s64_vv ; CHECK: liveins: $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; CHECK: %1:vreg_64 = nofpexcept V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; CHECK: $vgpr0_vgpr1 = COPY %1 %0:vgpr(s64) = COPY $vgpr0_vgpr1 %1:vgpr(s64) = G_FCEIL %0 $vgpr0_vgpr1 = COPY %1 ...