# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- name: ctpop_s32_ss legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $sgpr0 ; CHECK-LABEL: name: ctpop_s32_ss ; CHECK: liveins: $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[S_BCNT1_I32_B32_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B32 [[COPY]], implicit-def $scc ; CHECK: S_ENDPGM 0, implicit [[S_BCNT1_I32_B32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = G_CTPOP %0 S_ENDPGM 0, implicit %1 ... --- name: ctpop_s32_vs legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $sgpr0 ; CHECK-LABEL: name: ctpop_s32_vs ; CHECK: liveins: $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], 0, implicit $exec ; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]] %0:sgpr(s32) = COPY $sgpr0 %1:vgpr(s32) = G_CTPOP %0 S_ENDPGM 0, implicit %1 ... --- name: ctpop_s32_vv legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $vgpr0 ; CHECK-LABEL: name: ctpop_s32_vv ; CHECK: liveins: $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], 0, implicit $exec ; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]] %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = G_CTPOP %0 S_ENDPGM 0, implicit %1 ... --- name: add_ctpop_s32_v_vv_commute0 legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $vgpr0, $vgpr1 ; CHECK-LABEL: name: add_ctpop_s32_v_vv_commute0 ; CHECK: liveins: $vgpr0, $vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec ; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]] %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = G_CTPOP %0 %3:vgpr(s32) = G_ADD %2, %1 S_ENDPGM 0, implicit %3 ... --- name: add_ctpop_s32_v_vv_commute1 legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $vgpr0, $vgpr1 ; CHECK-LABEL: name: add_ctpop_s32_v_vv_commute1 ; CHECK: liveins: $vgpr0, $vgpr1 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec ; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]] %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr1 %2:vgpr(s32) = G_CTPOP %0 %3:vgpr(s32) = G_ADD %1, %2 S_ENDPGM 0, implicit %3 ... # Test add+ctpop pattern with all scalars. This should stay scalar. --- name: add_ctpop_s32_s_ss_commute0 legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $sgpr0, $sgpr1 ; CHECK-LABEL: name: add_ctpop_s32_s_ss_commute0 ; CHECK: liveins: $sgpr0, $sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; CHECK: [[S_BCNT1_I32_B32_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B32 [[COPY]], implicit-def $scc ; CHECK: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_BCNT1_I32_B32_]], [[COPY1]], implicit-def $scc ; CHECK: S_ENDPGM 0, implicit [[S_ADD_I32_]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr1 %2:sgpr(s32) = G_CTPOP %0 %3:sgpr(s32) = G_ADD %2, %1 S_ENDPGM 0, implicit %3 ... --- name: add_ctpop_s32_v_vs_commute0 legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $vgpr0, $sgpr0 ; CHECK-LABEL: name: add_ctpop_s32_v_vs_commute0 ; CHECK: liveins: $vgpr0, $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec ; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]] %0:vgpr(s32) = COPY $vgpr0 %1:sgpr(s32) = COPY $sgpr0 %2:vgpr(s32) = G_CTPOP %0 %3:vgpr(s32) = G_ADD %2, %1 S_ENDPGM 0, implicit %3 ... # SGPR->VGPR ctpop with VALU add --- name: add_ctpop_s32_v_sv_commute0 legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $vgpr0, $sgpr0 ; CHECK-LABEL: name: add_ctpop_s32_v_sv_commute0 ; CHECK: liveins: $vgpr0, $sgpr0 ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY1]], [[COPY]], implicit $exec ; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]] %0:vgpr(s32) = COPY $vgpr0 %1:sgpr(s32) = COPY $sgpr0 %2:vgpr(s32) = G_CTPOP %1 %3:vgpr(s32) = G_ADD %2, %0 S_ENDPGM 0, implicit %3 ... # Scalar ctpop with VALU add --- name: add_ctpop_s32_s_sv_commute0 legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $sgpr0, $vgpr0 ; CHECK-LABEL: name: add_ctpop_s32_s_sv_commute0 ; CHECK: liveins: $sgpr0, $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK: [[V_BCNT_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_BCNT_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec ; CHECK: S_ENDPGM 0, implicit [[V_BCNT_U32_B32_e64_]] %0:sgpr(s32) = COPY $sgpr0 %1:vgpr(s32) = COPY $vgpr0 %2:sgpr(s32) = G_CTPOP %0 %3:vgpr(s32) = G_ADD %2, %1 S_ENDPGM 0, implicit %3 ... --- name: ctpop_s64_ss legalized: true regBankSelected: true tracksRegLiveness: true body: | bb.0: liveins: $sgpr0_sgpr1 ; CHECK-LABEL: name: ctpop_s64_ss ; CHECK: liveins: $sgpr0_sgpr1 ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 ; CHECK: [[S_BCNT1_I32_B64_:%[0-9]+]]:sreg_32 = S_BCNT1_I32_B64 [[COPY]], implicit-def $scc ; CHECK: S_ENDPGM 0, implicit [[S_BCNT1_I32_B64_]] %0:sgpr(s64) = COPY $sgpr0_sgpr1 %1:sgpr(s32) = G_CTPOP %0 S_ENDPGM 0, implicit %1 ...