//===- MipsTargetMachine.h - Define TargetMachine for Mips ------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file declares the Mips specific subclass of TargetMachine. // //===----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H #define LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H #include "MCTargetDesc/MipsABIInfo.h" #include "MipsSubtarget.h" #include "llvm/ADT/Optional.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/CodeGen.h" #include "llvm/Target/TargetMachine.h" #include namespace llvm { class MipsTargetMachine : public LLVMTargetMachine { bool isLittle; std::unique_ptr TLOF; // Selected ABI MipsABIInfo ABI; const MipsSubtarget *Subtarget; MipsSubtarget DefaultSubtarget; MipsSubtarget NoMips16Subtarget; MipsSubtarget Mips16Subtarget; mutable StringMap> SubtargetMap; public: MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT, bool isLittle); ~MipsTargetMachine() override; TargetTransformInfo getTargetTransformInfo(const Function &F) override; const MipsSubtarget *getSubtargetImpl() const { if (Subtarget) return Subtarget; return &DefaultSubtarget; } const MipsSubtarget *getSubtargetImpl(const Function &F) const override; /// Reset the subtarget for the Mips target. void resetSubtarget(MachineFunction *MF); // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetLoweringObjectFile *getObjFileLowering() const override { return TLOF.get(); } /// Returns true if a cast between SrcAS and DestAS is a noop. bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { // Mips doesn't have any special address spaces so we just reserve // the first 256 for software use (e.g. OpenCL) and treat casts // between them as noops. return SrcAS < 256 && DestAS < 256; } bool isLittleEndian() const { return isLittle; } const MipsABIInfo &getABI() const { return ABI; } }; /// Mips32/64 big endian target machine. /// class MipsebTargetMachine : public MipsTargetMachine { virtual void anchor(); public: MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT); }; /// Mips32/64 little endian target machine. /// class MipselTargetMachine : public MipsTargetMachine { virtual void anchor(); public: MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional RM, Optional CM, CodeGenOpt::Level OL, bool JIT); }; } // end namespace llvm #endif // LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H