# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=armv8 -mcpu=cortex-a57 -instruction-tables < %s | FileCheck %s .text vabs.s8 d16, d16 vabs.s16 d16, d16 vabs.s32 d16, d16 vabs.f32 d16, d16 vabs.s8 q8, q8 vabs.s16 q8, q8 vabs.s32 q8, q8 vabs.f32 q8, q8 vqabs.s8 d16, d16 vqabs.s16 d16, d16 vqabs.s32 d16, d16 vqabs.s8 q8, q8 vqabs.s16 q8, q8 vqabs.s32 q8, q8 vabd.s8 d16, d16, d17 vabd.s16 d16, d16, d17 vabd.s32 d16, d16, d17 vabd.u8 d16, d16, d17 vabd.u16 d16, d16, d17 vabd.u32 d16, d16, d17 vabd.f32 d16, d16, d17 vabd.s8 q8, q8, q9 vabd.s16 q8, q8, q9 vabd.s32 q8, q8, q9 vabd.u8 q8, q8, q9 vabd.u16 q8, q8, q9 vabd.u32 q8, q8, q9 vabd.f32 q8, q8, q9 vabdl.s8 q8, d16, d17 vabdl.s16 q8, d16, d17 vabdl.s32 q8, d16, d17 vabdl.u8 q8, d16, d17 vabdl.u16 q8, d16, d17 vabdl.u32 q8, d16, d17 vaba.s8 d16, d18, d17 vaba.s16 d16, d18, d17 vaba.s32 d16, d18, d17 vaba.u8 d16, d18, d17 vaba.u16 d16, d18, d17 vaba.u32 d16, d18, d17 vaba.s8 q9, q8, q10 vaba.s16 q9, q8, q10 vaba.s32 q9, q8, q10 vaba.u8 q9, q8, q10 vaba.u16 q9, q8, q10 vaba.u32 q9, q8, q10 vabal.s8 q8, d19, d18 vabal.s16 q8, d19, d18 vabal.s32 q8, d19, d18 vabal.u8 q8, d19, d18 vabal.u16 q8, d19, d18 vabal.u32 q8, d19, d18 vadd.i8 d16, d17, d16 vadd.i16 d16, d17, d16 vadd.i64 d16, d17, d16 vadd.i32 d16, d17, d16 vadd.f32 d16, d16, d17 vadd.f32 q8, q8, q9 vaddl.s8 q8, d17, d16 vaddl.s16 q8, d17, d16 vaddl.s32 q8, d17, d16 vaddl.u8 q8, d17, d16 vaddl.u16 q8, d17, d16 vaddl.u32 q8, d17, d16 vaddw.s8 q8, q8, d18 vaddw.s16 q8, q8, d18 vaddw.s32 q8, q8, d18 vaddw.u8 q8, q8, d18 vaddw.u16 q8, q8, d18 vaddw.u32 q8, q8, d18 vhadd.s8 d16, d16, d17 vhadd.s16 d16, d16, d17 vhadd.s32 d16, d16, d17 vhadd.u8 d16, d16, d17 vhadd.u16 d16, d16, d17 vhadd.u32 d16, d16, d17 vhadd.s8 q8, q8, q9 vhadd.s16 q8, q8, q9 vhadd.s32 q8, q8, q9 vhadd.u8 q8, q8, q9 vhadd.u16 q8, q8, q9 vhadd.u32 q8, q8, q9 vrhadd.s8 d16, d16, d17 vrhadd.s16 d16, d16, d17 vrhadd.s32 d16, d16, d17 vrhadd.u8 d16, d16, d17 vrhadd.u16 d16, d16, d17 vrhadd.u32 d16, d16, d17 vrhadd.s8 q8, q8, q9 vrhadd.s16 q8, q8, q9 vrhadd.s32 q8, q8, q9 vrhadd.u8 q8, q8, q9 vrhadd.u16 q8, q8, q9 vrhadd.u32 q8, q8, q9 vqadd.s8 d16, d16, d17 vqadd.s16 d16, d16, d17 vqadd.s32 d16, d16, d17 vqadd.s64 d16, d16, d17 vqadd.u8 d16, d16, d17 vqadd.u16 d16, d16, d17 vqadd.u32 d16, d16, d17 vqadd.u64 d16, d16, d17 vqadd.s8 q8, q8, q9 vqadd.s16 q8, q8, q9 vqadd.s32 q8, q8, q9 vqadd.s64 q8, q8, q9 vqadd.u8 q8, q8, q9 vqadd.u16 q8, q8, q9 vqadd.u32 q8, q8, q9 vqadd.u64 q8, q8, q9 vaddhn.i16 d16, q8, q9 vaddhn.i32 d16, q8, q9 vaddhn.i64 d16, q8, q9 vraddhn.i16 d16, q8, q9 vraddhn.i32 d16, q8, q9 vraddhn.i64 d16, q8, q9 vcnt.8 d16, d16 vcnt.8 q8, q8 vclz.i8 d16, d16 vclz.i16 d16, d16 vclz.i32 d16, d16 vclz.i8 q8, q8 vclz.i16 q8, q8 vclz.i32 q8, q8 vcls.s8 d16, d16 vcls.s16 d16, d16 vcls.s32 d16, d16 vcls.s8 q8, q8 vcls.s16 q8, q8 vcls.s32 q8, q8 vand d16, d17, d16 vand q8, q8, q9 veor d16, d17, d16 veor q8, q8, q9 vorr d16, d17, d16 vorr q8, q8, q9 vorr.i32 d16, #0x1000000 vorr.i32 q8, #0x1000000 vorr.i32 q8, #0x0 vbic d16, d17, d16 vbic q8, q8, q9 vbic.i32 d16, #0xff000000 vbic.i32 q8, #0xff000000 vorn d16, d17, d16 vorn q8, q8, q9 vmvn d16, d16 vmvn q8, q8 vbsl d18, d17, d16 vbsl q8, q10, q9 vbit d18, d17, d16 vbit q8, q10, q9 vbif d18, d17, d16 vbif q8, q10, q9 vceq.i8 d16, d16, d17 vceq.i16 d16, d16, d17 vceq.i32 d16, d16, d17 vceq.f32 d16, d16, d17 vceq.i8 q8, q8, q9 vceq.i16 q8, q8, q9 vceq.i32 q8, q8, q9 vceq.f32 q8, q8, q9 vcge.s8 d16, d16, d17 vcge.s16 d16, d16, d17 vcge.s32 d16, d16, d17 vcge.u8 d16, d16, d17 vcge.u16 d16, d16, d17 vcge.u32 d16, d16, d17 vcge.f32 d16, d16, d17 vcge.s8 q8, q8, q9 vcge.s16 q8, q8, q9 vcge.s32 q8, q8, q9 vcge.u8 q8, q8, q9 vcge.u16 q8, q8, q9 vcge.u32 q8, q8, q9 vcge.f32 q8, q8, q9 vacge.f32 d16, d16, d17 vacge.f32 q8, q8, q9 vcgt.s8 d16, d16, d17 vcgt.s16 d16, d16, d17 vcgt.s32 d16, d16, d17 vcgt.u8 d16, d16, d17 vcgt.u16 d16, d16, d17 vcgt.u32 d16, d16, d17 vcgt.f32 d16, d16, d17 vcgt.s8 q8, q8, q9 vcgt.s16 q8, q8, q9 vcgt.s32 q8, q8, q9 vcgt.u8 q8, q8, q9 vcgt.u16 q8, q8, q9 vcgt.u32 q8, q8, q9 vcgt.f32 q8, q8, q9 vacgt.f32 d16, d16, d17 vacgt.f32 q8, q8, q9 vtst.8 d16, d16, d17 vtst.16 d16, d16, d17 vtst.32 d16, d16, d17 vtst.8 q8, q8, q9 vtst.16 q8, q8, q9 vtst.32 q8, q8, q9 vceq.i8 d16, d16, #0 vcge.s8 d16, d16, #0 vcle.s8 d16, d16, #0 vcgt.s8 d16, d16, #0 vclt.s8 d16, d16, #0 vcvt.s32.f32 d16, d16 vcvt.u32.f32 d16, d16 vcvt.f32.s32 d16, d16 vcvt.f32.u32 d16, d16 vcvt.s32.f32 q8, q8 vcvt.u32.f32 q8, q8 vcvt.f32.s32 q8, q8 vcvt.f32.u32 q8, q8 vcvt.s32.f32 d16, d16, #1 vcvt.u32.f32 d16, d16, #1 vcvt.f32.s32 d16, d16, #1 vcvt.f32.u32 d16, d16, #1 vcvt.s32.f32 q8, q8, #1 vcvt.u32.f32 q8, q8, #1 vcvt.f32.s32 q8, q8, #1 vcvt.f32.u32 q8, q8, #1 vcvt.f32.f16 q8, d16 vcvt.f16.f32 d16, q8 vdup.8 d16, r0 vdup.16 d16, r0 vdup.32 d16, r0 vdup.8 q8, r0 vdup.16 q8, r0 vdup.32 q8, r0 vdup.8 d16, d16[1] vdup.16 d16, d16[1] vdup.32 d16, d16[1] vdup.8 q8, d16[1] vdup.16 q8, d16[1] vdup.32 q8, d16[1] vmin.s8 d16, d16, d17 vmin.s16 d16, d16, d17 vmin.s32 d16, d16, d17 vmin.u8 d16, d16, d17 vmin.u16 d16, d16, d17 vmin.u32 d16, d16, d17 vmin.f32 d16, d16, d17 vmin.s8 q8, q8, q9 vmin.s16 q8, q8, q9 vmin.s32 q8, q8, q9 vmin.u8 q8, q8, q9 vmin.u16 q8, q8, q9 vmin.u32 q8, q8, q9 vmin.f32 q8, q8, q9 vmax.s8 d16, d16, d17 vmax.s16 d16, d16, d17 vmax.s32 d16, d16, d17 vmax.u8 d16, d16, d17 vmax.u16 d16, d16, d17 vmax.u32 d16, d16, d17 vmax.f32 d16, d16, d17 vmax.s8 q8, q8, q9 vmax.s16 q8, q8, q9 vmax.s32 q8, q8, q9 vmax.u8 q8, q8, q9 vmax.u16 q8, q8, q9 vmax.u32 q8, q8, q9 vmax.f32 q8, q8, q9 vmov.i8 d16, #0x8 vmov.i16 d16, #0x10 vmov.i16 d16, #0x1000 vmov.i32 d16, #0x20 vmov.i32 d16, #0x2000 vmov.i32 d16, #0x200000 vmov.i32 d16, #0x20000000 vmov.i32 d16, #0x20ff vmov.i32 d16, #0x20ffff vmov.i64 d16, #0xff0000ff0000ffff vmov.i8 q8, #0x8 vmov.i16 q8, #0x10 vmov.i16 q8, #0x1000 vmov.i32 q8, #0x20 vmov.i32 q8, #0x2000 vmov.i32 q8, #0x200000 vmov.i32 q8, #0x20000000 vmov.i32 q8, #0x20ff vmov.i32 q8, #0x20ffff vmov.i64 q8, #0xff0000ff0000ffff vmvn.i16 d16, #0x10 vmvn.i16 d16, #0x1000 vmvn.i32 d16, #0x20 vmvn.i32 d16, #0x2000 vmvn.i32 d16, #0x200000 vmvn.i32 d16, #0x20000000 vmvn.i32 d16, #0x20ff vmvn.i32 d16, #0x20ffff vmovl.s8 q8, d16 vmovl.s16 q8, d16 vmovl.s32 q8, d16 vmovl.u8 q8, d16 vmovl.u16 q8, d16 vmovl.u32 q8, d16 vmovn.i16 d16, q8 vmovn.i32 d16, q8 vmovn.i64 d16, q8 vqmovn.s16 d16, q8 vqmovn.s32 d16, q8 vqmovn.s64 d16, q8 vqmovn.u16 d16, q8 vqmovn.u32 d16, q8 vqmovn.u64 d16, q8 vqmovun.s16 d16, q8 vqmovun.s32 d16, q8 vqmovun.s64 d16, q8 vmov.s8 r0, d16[1] vmov.s16 r0, d16[1] vmov.u8 r0, d16[1] vmov.u16 r0, d16[1] vmov.32 r0, d16[1] vmov.8 d16[1], r1 vmov.16 d16[1], r1 vmov.32 d16[1], r1 vmov.8 d18[1], r1 vmov.16 d18[1], r1 vmov.32 d18[1], r1 vmla.i8 d16, d18, d17 vmla.i16 d16, d18, d17 vmla.i32 d16, d18, d17 vmla.f32 d16, d18, d17 vmla.i8 q9, q8, q10 vmla.i16 q9, q8, q10 vmla.i32 q9, q8, q10 vmla.f32 q9, q8, q10 vmlal.s8 q8, d19, d18 vmlal.s16 q8, d19, d18 vmlal.s32 q8, d19, d18 vmlal.u8 q8, d19, d18 vmlal.u16 q8, d19, d18 vmlal.u32 q8, d19, d18 vqdmlal.s16 q8, d19, d18 vqdmlal.s32 q8, d19, d18 vmls.i8 d16, d18, d17 vmls.i16 d16, d18, d17 vmls.i32 d16, d18, d17 vmls.f32 d16, d18, d17 vmls.i8 q9, q8, q10 vmls.i16 q9, q8, q10 vmls.i32 q9, q8, q10 vmls.f32 q9, q8, q10 vmlsl.s8 q8, d19, d18 vmlsl.s16 q8, d19, d18 vmlsl.s32 q8, d19, d18 vmlsl.u8 q8, d19, d18 vmlsl.u16 q8, d19, d18 vmlsl.u32 q8, d19, d18 vqdmlsl.s16 q8, d19, d18 vqdmlsl.s32 q8, d19, d18 vmul.i8 d16, d16, d17 vmul.i16 d16, d16, d17 vmul.i32 d16, d16, d17 vmul.f32 d16, d16, d17 vmul.i8 q8, q8, q9 vmul.i16 q8, q8, q9 vmul.i32 q8, q8, q9 vmul.f32 q8, q8, q9 vmul.p8 d16, d16, d17 vmul.p8 q8, q8, q9 vqdmulh.s16 d16, d16, d17 vqdmulh.s32 d16, d16, d17 vqdmulh.s16 q8, q8, q9 vqdmulh.s32 q8, q8, q9 vqrdmulh.s16 d16, d16, d17 vqrdmulh.s32 d16, d16, d17 vqrdmulh.s16 q8, q8, q9 vqrdmulh.s32 q8, q8, q9 vmull.s8 q8, d16, d17 vmull.s16 q8, d16, d17 vmull.s32 q8, d16, d17 vmull.u8 q8, d16, d17 vmull.u16 q8, d16, d17 vmull.u32 q8, d16, d17 vmull.p8 q8, d16, d17 vqdmull.s16 q8, d16, d17 vqdmull.s32 q8, d16, d17 vneg.s8 d16, d16 vneg.s16 d16, d16 vneg.s32 d16, d16 vneg.f32 d16, d16 vneg.s8 q8, q8 vneg.s16 q8, q8 vneg.s32 q8, q8 vneg.f32 q8, q8 vqneg.s8 d16, d16 vqneg.s16 d16, d16 vqneg.s32 d16, d16 vqneg.s8 q8, q8 vqneg.s16 q8, q8 vqneg.s32 q8, q8 vpadd.i8 d16, d17, d16 vpadd.i16 d16, d17, d16 vpadd.i32 d16, d17, d16 vpadd.f32 d16, d16, d17 vpaddl.s8 d16, d16 vpaddl.s16 d16, d16 vpaddl.s32 d16, d16 vpaddl.u8 d16, d16 vpaddl.u16 d16, d16 vpaddl.u32 d16, d16 vpaddl.s8 q8, q8 vpaddl.s16 q8, q8 vpaddl.s32 q8, q8 vpaddl.u8 q8, q8 vpaddl.u16 q8, q8 vpaddl.u32 q8, q8 vpadal.s8 d16, d17 vpadal.s16 d16, d17 vpadal.s32 d16, d17 vpadal.u8 d16, d17 vpadal.u16 d16, d17 vpadal.u32 d16, d17 vpadal.s8 q9, q8 vpadal.s16 q9, q8 vpadal.s32 q9, q8 vpadal.u8 q9, q8 vpadal.u16 q9, q8 vpadal.u32 q9, q8 vpmin.s8 d16, d16, d17 vpmin.s16 d16, d16, d17 vpmin.s32 d16, d16, d17 vpmin.u8 d16, d16, d17 vpmin.u16 d16, d16, d17 vpmin.u32 d16, d16, d17 vpmin.f32 d16, d16, d17 vpmax.s8 d16, d16, d17 vpmax.s16 d16, d16, d17 vpmax.s32 d16, d16, d17 vpmax.u8 d16, d16, d17 vpmax.u16 d16, d16, d17 vpmax.u32 d16, d16, d17 vpmax.f32 d16, d16, d17 vrecpe.u32 d16, d16 vrecpe.u32 q8, q8 vrecpe.f32 d16, d16 vrecpe.f32 q8, q8 vrecps.f32 d16, d16, d17 vrecps.f32 q8, q8, q9 vrsqrte.u32 d16, d16 vrsqrte.u32 q8, q8 vrsqrte.f32 d16, d16 vrsqrte.f32 q8, q8 vrsqrts.f32 d16, d16, d17 vrsqrts.f32 q8, q8, q9 vrev64.8 d16, d16 vrev64.16 d16, d16 vrev64.32 d16, d16 vrev64.8 q8, q8 vrev64.16 q8, q8 vrev64.32 q8, q8 vrev32.8 d16, d16 vrev32.16 d16, d16 vrev32.8 q8, q8 vrev32.16 q8, q8 vrev16.8 d16, d16 vrev16.8 q8, q8 vqshl.s8 d16, d16, d17 vqshl.s16 d16, d16, d17 vqshl.s32 d16, d16, d17 vqshl.s64 d16, d16, d17 vqshl.u8 d16, d16, d17 vqshl.u16 d16, d16, d17 vqshl.u32 d16, d16, d17 vqshl.u64 d16, d16, d17 vqshl.s8 q8, q8, q9 vqshl.s16 q8, q8, q9 vqshl.s32 q8, q8, q9 vqshl.s64 q8, q8, q9 vqshl.u8 q8, q8, q9 vqshl.u16 q8, q8, q9 vqshl.u32 q8, q8, q9 vqshl.u64 q8, q8, q9 vqshl.s8 d16, d16, #7 vqshl.s16 d16, d16, #15 vqshl.s32 d16, d16, #31 vqshl.s64 d16, d16, #63 vqshl.u8 d16, d16, #7 vqshl.u16 d16, d16, #15 vqshl.u32 d16, d16, #31 vqshl.u64 d16, d16, #63 vqshlu.s8 d16, d16, #7 vqshlu.s16 d16, d16, #15 vqshlu.s32 d16, d16, #31 vqshlu.s64 d16, d16, #63 vqshl.s8 q8, q8, #7 vqshl.s16 q8, q8, #15 vqshl.s32 q8, q8, #31 vqshl.s64 q8, q8, #63 vqshl.u8 q8, q8, #7 vqshl.u16 q8, q8, #15 vqshl.u32 q8, q8, #31 vqshl.u64 q8, q8, #63 vqshlu.s8 q8, q8, #7 vqshlu.s16 q8, q8, #15 vqshlu.s32 q8, q8, #31 vqshlu.s64 q8, q8, #63 vqrshl.s8 d16, d16, d17 vqrshl.s16 d16, d16, d17 vqrshl.s32 d16, d16, d17 vqrshl.s64 d16, d16, d17 vqrshl.u8 d16, d16, d17 vqrshl.u16 d16, d16, d17 vqrshl.u32 d16, d16, d17 vqrshl.u64 d16, d16, d17 vqrshl.s8 q8, q8, q9 vqrshl.s16 q8, q8, q9 vqrshl.s32 q8, q8, q9 vqrshl.s64 q8, q8, q9 vqrshl.u8 q8, q8, q9 vqrshl.u16 q8, q8, q9 vqrshl.u32 q8, q8, q9 vqrshl.u64 q8, q8, q9 vqshrn.s16 d16, q8, #8 vqshrn.s32 d16, q8, #16 vqshrn.s64 d16, q8, #32 vqshrn.u16 d16, q8, #8 vqshrn.u32 d16, q8, #16 vqshrn.u64 d16, q8, #32 vqshrun.s16 d16, q8, #8 vqshrun.s32 d16, q8, #16 vqshrun.s64 d16, q8, #32 vqrshrn.s16 d16, q8, #8 vqrshrn.s32 d16, q8, #16 vqrshrn.s64 d16, q8, #32 vqrshrn.u16 d16, q8, #8 vqrshrn.u32 d16, q8, #16 vqrshrn.u64 d16, q8, #32 vqrshrun.s16 d16, q8, #8 vqrshrun.s32 d16, q8, #16 vqrshrun.s64 d16, q8, #32 vshl.u8 d16, d17, d16 vshl.u16 d16, d17, d16 vshl.u32 d16, d17, d16 vshl.u64 d16, d17, d16 vshl.i8 d16, d16, #7 vshl.i16 d16, d16, #15 vshl.i32 d16, d16, #31 vshl.i64 d16, d16, #63 vshl.u8 q8, q9, q8 vshl.u16 q8, q9, q8 vshl.u32 q8, q9, q8 vshl.u64 q8, q9, q8 vshl.i8 q8, q8, #7 vshl.i16 q8, q8, #15 vshl.i32 q8, q8, #31 vshl.i64 q8, q8, #63 vshr.u8 d16, d16, #7 vshr.u16 d16, d16, #15 vshr.u32 d16, d16, #31 vshr.u64 d16, d16, #63 vshr.u8 q8, q8, #7 vshr.u16 q8, q8, #15 vshr.u32 q8, q8, #31 vshr.u64 q8, q8, #63 vshr.s8 d16, d16, #7 vshr.s16 d16, d16, #15 vshr.s32 d16, d16, #31 vshr.s64 d16, d16, #63 vshr.s8 q8, q8, #7 vshr.s16 q8, q8, #15 vshr.s32 q8, q8, #31 vshr.s64 q8, q8, #63 vsra.u8 d16, d16, #7 vsra.u16 d16, d16, #15 vsra.u32 d16, d16, #31 vsra.u64 d16, d16, #63 vsra.u8 q8, q8, #7 vsra.u16 q8, q8, #15 vsra.u32 q8, q8, #31 vsra.u64 q8, q8, #63 vsra.s8 d16, d16, #7 vsra.s16 d16, d16, #15 vsra.s32 d16, d16, #31 vsra.s64 d16, d16, #63 vsra.s8 q8, q8, #7 vsra.s16 q8, q8, #15 vsra.s32 q8, q8, #31 vsra.s64 q8, q8, #63 vsri.8 d16, d16, #7 vsri.16 d16, d16, #15 vsri.32 d16, d16, #31 vsri.64 d16, d16, #63 vsri.8 q8, q8, #7 vsri.16 q8, q8, #15 vsri.32 q8, q8, #31 vsri.64 q8, q8, #63 vsli.8 d16, d16, #7 vsli.16 d16, d16, #15 vsli.32 d16, d16, #31 vsli.64 d16, d16, #63 vsli.8 q8, q8, #7 vsli.16 q8, q8, #15 vsli.32 q8, q8, #31 vsli.64 q8, q8, #63 vshll.s8 q8, d16, #7 vshll.s16 q8, d16, #15 vshll.s32 q8, d16, #31 vshll.u8 q8, d16, #7 vshll.u16 q8, d16, #15 vshll.u32 q8, d16, #31 vshll.i8 q8, d16, #8 vshll.i16 q8, d16, #16 vshll.i32 q8, d16, #32 vshrn.i16 d16, q8, #8 vshrn.i32 d16, q8, #16 vshrn.i64 d16, q8, #32 vrshl.s8 d16, d17, d16 vrshl.s16 d16, d17, d16 vrshl.s32 d16, d17, d16 vrshl.s64 d16, d17, d16 vrshl.u8 d16, d17, d16 vrshl.u16 d16, d17, d16 vrshl.u32 d16, d17, d16 vrshl.u64 d16, d17, d16 vrshl.s8 q8, q9, q8 vrshl.s16 q8, q9, q8 vrshl.s32 q8, q9, q8 vrshl.s64 q8, q9, q8 vrshl.u8 q8, q9, q8 vrshl.u16 q8, q9, q8 vrshl.u32 q8, q9, q8 vrshl.u64 q8, q9, q8 vrshr.s8 d16, d16, #8 vrshr.s16 d16, d16, #16 vrshr.s32 d16, d16, #32 vrshr.s64 d16, d16, #64 vrshr.u8 d16, d16, #8 vrshr.u16 d16, d16, #16 vrshr.u32 d16, d16, #32 vrshr.u64 d16, d16, #64 vrshr.s8 q8, q8, #8 vrshr.s16 q8, q8, #16 vrshr.s32 q8, q8, #32 vrshr.s64 q8, q8, #64 vrshr.u8 q8, q8, #8 vrshr.u16 q8, q8, #16 vrshr.u32 q8, q8, #32 vrshr.u64 q8, q8, #64 vrshrn.i16 d16, q8, #8 vrshrn.i32 d16, q8, #16 vrshrn.i64 d16, q8, #32 vqrshrn.s16 d16, q8, #4 vqrshrn.s32 d16, q8, #13 vqrshrn.s64 d16, q8, #13 vqrshrn.u16 d16, q8, #4 vqrshrn.u32 d16, q8, #13 vqrshrn.u64 d16, q8, #13 vsra.s8 d17, d16, #8 vsra.s16 d17, d16, #16 vsra.s32 d17, d16, #32 vsra.s64 d17, d16, #64 vsra.s8 q8, q9, #8 vsra.s16 q8, q9, #16 vsra.s32 q8, q9, #32 vsra.s64 q8, q9, #64 vsra.u8 d17, d16, #8 vsra.u16 d17, d16, #16 vsra.u32 d17, d16, #32 vsra.u64 d17, d16, #64 vsra.u8 q8, q9, #8 vsra.u16 q8, q9, #16 vsra.u32 q8, q9, #32 vsra.u64 q8, q9, #64 vrsra.s8 d17, d16, #8 vrsra.s16 d17, d16, #16 vrsra.s32 d17, d16, #32 vrsra.s64 d17, d16, #64 vrsra.u8 d17, d16, #8 vrsra.u16 d17, d16, #16 vrsra.u32 d17, d16, #32 vrsra.u64 d17, d16, #64 vrsra.s8 q8, q9, #8 vrsra.s16 q8, q9, #16 vrsra.s32 q8, q9, #32 vrsra.s64 q8, q9, #64 vrsra.u8 q8, q9, #8 vrsra.u16 q8, q9, #16 vrsra.u32 q8, q9, #32 vrsra.u64 q8, q9, #64 vsli.8 d17, d16, #7 vsli.16 d17, d16, #15 vsli.32 d17, d16, #31 vsli.64 d17, d16, #63 vsli.8 q9, q8, #7 vsli.16 q9, q8, #15 vsli.32 q9, q8, #31 vsli.64 q9, q8, #63 vsri.8 d17, d16, #8 vsri.16 d17, d16, #16 vsri.32 d17, d16, #32 vsri.64 d17, d16, #64 vsri.8 q9, q8, #8 vsri.16 q9, q8, #16 vsri.32 q9, q8, #32 vsri.64 q9, q8, #64 vext.8 d16, d17, d16, #3 vext.8 d16, d17, d16, #5 vext.8 q8, q9, q8, #3 vext.8 q8, q9, q8, #7 vext.16 d16, d17, d16, #3 vext.32 q8, q9, q8, #3 vtrn.8 d17, d16 vtrn.16 d17, d16 vtrn.32 d17, d16 vtrn.8 q9, q8 vtrn.16 q9, q8 vtrn.32 q9, q8 vuzp.8 d17, d16 vuzp.16 d17, d16 vuzp.8 q9, q8 vuzp.16 q9, q8 vuzp.32 q9, q8 vzip.8 d17, d16 vzip.16 d17, d16 vzip.8 q9, q8 vzip.16 q9, q8 vzip.32 q9, q8 vsub.i8 d16, d17, d16 vsub.i16 d16, d17, d16 vsub.i32 d16, d17, d16 vsub.i64 d16, d17, d16 vsub.f32 d16, d16, d17 vsub.i8 q8, q8, q9 vsub.i16 q8, q8, q9 vsub.i32 q8, q8, q9 vsub.i64 q8, q8, q9 vsub.f32 q8, q8, q9 vsubl.s8 q8, d17, d16 vsubl.s16 q8, d17, d16 vsubl.s32 q8, d17, d16 vsubl.u8 q8, d17, d16 vsubl.u16 q8, d17, d16 vsubl.u32 q8, d17, d16 vsubw.s8 q8, q8, d18 vsubw.s16 q8, q8, d18 vsubw.s32 q8, q8, d18 vsubw.u8 q8, q8, d18 vsubw.u16 q8, q8, d18 vsubw.u32 q8, q8, d18 vhsub.s8 d16, d16, d17 vhsub.s16 d16, d16, d17 vhsub.s32 d16, d16, d17 vhsub.u8 d16, d16, d17 vhsub.u16 d16, d16, d17 vhsub.u32 d16, d16, d17 vhsub.s8 q8, q8, q9 vhsub.s16 q8, q8, q9 vhsub.s32 q8, q8, q9 vqsub.s8 d16, d16, d17 vqsub.s16 d16, d16, d17 vqsub.s32 d16, d16, d17 vqsub.s64 d16, d16, d17 vqsub.u8 d16, d16, d17 vqsub.u16 d16, d16, d17 vqsub.u32 d16, d16, d17 vqsub.u64 d16, d16, d17 vqsub.s8 q8, q8, q9 vqsub.s16 q8, q8, q9 vqsub.s32 q8, q8, q9 vqsub.s64 q8, q8, q9 vqsub.u8 q8, q8, q9 vqsub.u16 q8, q8, q9 vqsub.u32 q8, q8, q9 vqsub.u64 q8, q8, q9 vsubhn.i16 d16, q8, q9 vsubhn.i32 d16, q8, q9 vsubhn.i64 d16, q8, q9 vrsubhn.i16 d16, q8, q9 vrsubhn.i32 d16, q8, q9 vrsubhn.i64 d16, q8, q9 vtbl.8 d16, {d17}, d16 vtbl.8 d16, {d16, d17}, d18 vtbl.8 d16, {d16, d17, d18}, d20 vtbl.8 d16, {d16, d17, d18, d19}, d20 vtbx.8 d18, {d16}, d17 vtbx.8 d19, {d16, d17}, d18 vtbx.8 d20, {d16, d17, d18}, d21 vtbx.8 d20, {d16, d17, d18, d19}, d21 vld1.8 {d16}, [r0:64] vld1.16 {d16}, [r0] vld1.32 {d16}, [r0] vld1.64 {d16}, [r0] vld1.8 {d16, d17}, [r0:64] vld1.16 {d16, d17}, [r0:128] vld1.32 {d16, d17}, [r0] vld1.64 {d16, d17}, [r0] vld2.8 {d16, d17}, [r0:64] vld2.16 {d16, d17}, [r0:128] vld2.32 {d16, d17}, [r0] vld2.8 {d16, d17, d18, d19}, [r0:64] vld2.16 {d16, d17, d18, d19}, [r0:128] vld2.32 {d16, d17, d18, d19}, [r0:256] vld3.8 {d16, d17, d18}, [r0:64] vld3.16 {d16, d17, d18}, [r0] vld3.32 {d16, d17, d18}, [r0] vld3.8 {d16, d18, d20}, [r0:64]! vld3.8 {d17, d19, d21}, [r0:64]! vld3.16 {d16, d18, d20}, [r0]! vld3.16 {d17, d19, d21}, [r0]! vld3.32 {d16, d18, d20}, [r0]! vld3.32 {d17, d19, d21}, [r0]! vld4.8 {d16, d17, d18, d19}, [r0:64] vld4.16 {d16, d17, d18, d19}, [r0:128] vld4.32 {d16, d17, d18, d19}, [r0:256] vld4.8 {d16, d18, d20, d22}, [r0:256]! vld4.8 {d17, d19, d21, d23}, [r0:256]! vld4.16 {d16, d18, d20, d22}, [r0]! vld4.16 {d17, d19, d21, d23}, [r0]! vld4.32 {d16, d18, d20, d22}, [r0]! vld4.32 {d17, d19, d21, d23}, [r0]! vld1.8 {d16[3]}, [r0] vld1.16 {d16[2]}, [r0:16] vld1.32 {d16[1]}, [r0:32] vld2.8 {d16[1], d17[1]}, [r0:16] vld2.16 {d16[1], d17[1]}, [r0:32] vld2.32 {d16[1], d17[1]}, [r0] vld2.16 {d17[1], d19[1]}, [r0] vld2.32 {d17[0], d19[0]}, [r0:64] vld3.8 {d16[1], d17[1], d18[1]}, [r0] vld3.16 {d16[1], d17[1], d18[1]}, [r0] vld3.32 {d16[1], d17[1], d18[1]}, [r0] vld3.16 {d16[1], d18[1], d20[1]}, [r0] vld3.32 {d17[1], d19[1], d21[1]}, [r0] vld3.8 {d0[], d1[], d2[]}, [r4] vld3.8 {d0[], d1[], d2[]}, [r4]! vld3.8 {d0[], d2[], d4[]}, [r4], r5 vld3.16 {d0[], d2[], d4[]}, [r4] vld3.16 {d0[], d1[], d2[]}, [r4]! vld3.16 {d0[], d2[], d4[]}, [r4], r5 vld3.32 {d0[], d1[], d2[]}, [r4] vld3.32 {d0[], d1[], d2[]}, [r4]! vld3.32 {d0[], d2[], d4[]}, [r4], r5 vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] vld4.8 {d0[], d1[], d2[], d3[]}, [r4] vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r5 vld4.16 {d0[], d1[], d2[], d3[]}, [r4] vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r5 vld4.32 {d0[], d1[], d2[], d3[]}, [r4] vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r5 vst1.8 {d16}, [r0:64] vst1.16 {d16}, [r0] vst1.32 {d16}, [r0] vst1.64 {d16}, [r0] vst1.8 {d16, d17}, [r0:64] vst1.16 {d16, d17}, [r0:128] vst1.32 {d16, d17}, [r0] vst1.64 {d16, d17}, [r0] vst2.8 {d16, d17}, [r0:64] vst2.16 {d16, d17}, [r0:128] vst2.32 {d16, d17}, [r0] vst2.8 {d16, d17, d18, d19}, [r0:64] vst2.16 {d16, d17, d18, d19}, [r0:128] vst2.32 {d16, d17, d18, d19}, [r0:256] vst3.8 {d16, d17, d18}, [r0:64] vst3.16 {d16, d17, d18}, [r0] vst3.32 {d16, d17, d18}, [r0] vst3.8 {d16, d18, d20}, [r0:64]! vst3.8 {d17, d19, d21}, [r0:64]! vst3.16 {d16, d18, d20}, [r0]! vst3.16 {d17, d19, d21}, [r0]! vst3.32 {d16, d18, d20}, [r0]! vst3.32 {d17, d19, d21}, [r0]! vst4.8 {d16, d17, d18, d19}, [r0:64] vst4.16 {d16, d17, d18, d19}, [r0:128] vst4.8 {d16, d18, d20, d22}, [r0:256]! vst4.8 {d17, d19, d21, d23}, [r0:256]! vst4.16 {d16, d18, d20, d22}, [r0]! vst4.16 {d17, d19, d21, d23}, [r0]! vst4.32 {d16, d18, d20, d22}, [r0]! vst4.32 {d17, d19, d21, d23}, [r0]! vst2.8 {d16[1], d17[1]}, [r0:16] vst2.16 {d16[1], d17[1]}, [r0:32] vst2.32 {d16[1], d17[1]}, [r0] vst2.16 {d17[1], d19[1]}, [r0] vst2.32 {d17[0], d19[0]}, [r0:64] vst3.8 {d16[1], d17[1], d18[1]}, [r0] vst3.16 {d16[1], d17[1], d18[1]}, [r0] vst3.32 {d16[1], d17[1], d18[1]}, [r0] vst3.16 {d17[2], d19[2], d21[2]}, [r0] vst3.32 {d16[0], d18[0], d20[0]}, [r0] vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] vld1.8 {d0[]}, [r0], r0 vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! vmovvs r2, lr, s27, s28 vmov s3, s4, r1, r2 vmov s2, s3, r1, r2 vmov r1, r2, s3, s4 vmov r1, r2, s2, s3 vmov d15, r1, r2 vmov d16, r1, r2 vmov r1, r2, d15 vmov r1, r2, d16 vcvttmi.f32.f16 s2, s19 vld1.8 {d23, d24, d25}, [r6:64]! vld1.32 {d22, d23, d24, d25}, [pc:64]! vst1.32 {d26, d27}, [r1:64]! vmov.f32 d0, #1.600000e+01 vmov.f32 q0, #1.600000e+01 vst1.8 {d8}, [r4]! vst1.16 {d8}, [r4]! vst1.32 {d8}, [r4]! vst1.64 {d8}, [r4]! vst1.8 {d8}, [r4], r6 vst1.16 {d8}, [r4], r6 vst1.32 {d8}, [r4], r6 vst1.64 {d8}, [r4], r6 vst1.8 {d8, d9}, [r4]! vst1.16 {d8, d9}, [r4]! vst1.32 {d8, d9}, [r4]! vst1.64 {d8, d9}, [r4]! vst1.8 {d8, d9}, [r4], r6 vst1.16 {d8, d9}, [r4], r6 vst1.32 {d8, d9}, [r4], r6 vst1.64 {d8, d9}, [r4], r6 vst1.8 {d8, d9, d10}, [r4]! vst1.16 {d8, d9, d10}, [r4]! vst1.32 {d8, d9, d10}, [r4]! vst1.64 {d8, d9, d10}, [r4]! vst1.8 {d8, d9, d10}, [r4], r6 vst1.16 {d8, d9, d10}, [r4], r6 vst1.32 {d8, d9, d10}, [r4], r6 vst1.64 {d8, d9, d10}, [r4], r6 vst1.8 {d8, d9, d10, d11}, [r4]! vst1.16 {d8, d9, d10, d11}, [r4]! vst1.32 {d8, d9, d10, d11}, [r4]! vst1.64 {d8, d9, d10, d11}, [r4]! vst1.8 {d8, d9, d10, d11}, [r4], r6 vst1.16 {d8, d9, d10, d11}, [r4], r6 vst1.32 {d8, d9, d10, d11}, [r4], r6 vst1.64 {d8, d9, d10, d11}, [r4], r6 vst2.8 {d8, d9}, [r4]! vst2.16 {d8, d9}, [r4]! vst2.32 {d8, d9}, [r4]! vst2.8 {d8, d9}, [r4], r6 vst2.16 {d8, d9}, [r4], r6 vst2.32 {d8, d9}, [r4], r6 vst2.8 {d8, d10}, [r4]! vst2.16 {d8, d10}, [r4]! vst2.32 {d8, d10}, [r4]! vst2.8 {d8, d10}, [r4], r6 vst2.16 {d8, d10}, [r4], r6 vst2.32 {d8, d10}, [r4], r6 vst3.8 {d8, d9, d10}, [r4]! vst3.16 {d8, d9, d10}, [r4]! vst3.32 {d8, d9, d10}, [r4]! vst3.8 {d8, d10, d12}, [r4], r6 vst3.16 {d8, d10, d12}, [r4], r6 vst3.32 {d8, d10, d12}, [r4], r6 vst4.8 {d8, d9, d10, d11}, [r4]! vst4.16 {d8, d9, d10, d11}, [r4]! vst4.32 {d8, d9, d10, d11}, [r4]! vst4.8 {d8, d10, d12, d14}, [r4], r6 vst4.16 {d8, d10, d12, d14}, [r4], r6 vst4.32 {d8, d10, d12, d14}, [r4], r6 vst1.16 {d8, d9}, [r4] vst1.32 {d8, d9}, [r4] vst1.64 {d8, d9}, [r4] vst1.8 {d8, d9}, [r4] vst2.16 {d8, d9}, [r4] vst2.32 {d8, d9}, [r4] vst2.8 {d8, d9}, [r4] vst2.16 {d8, d9}, [r4]! vst2.16 {d8, d9}, [r4], r6 vst2.32 {d8, d9}, [r4]! vst2.32 {d8, d9}, [r4], r6 vst2.8 {d8, d9}, [r4]! vst2.8 {d8, d9}, [r4], r6 vst2.16 {d8, d10}, [r4] vst2.32 {d8, d10}, [r4] vst2.8 {d8, d10}, [r4] vst3.8 {d8, d9, d10}, [r4] vst3.16 {d8, d9, d10}, [r4] vst3.32 {d8, d9, d10}, [r4] vst4.8 {d8, d9, d10, d11}, [r4] vst4.16 {d8, d9, d10, d11}, [r4] vst4.32 {d8, d9, d10, d11}, [r4] vst3.8 {d8, d10, d12}, [r4] vst3.16 {d8, d10, d12}, [r4] vst3.32 {d8, d10, d12}, [r4] vst4.8 {d8, d10, d12, d14}, [r4] vst4.16 {d8, d10, d12, d14}, [r4] vst4.32 {d8, d10, d12, d14}, [r4] vld1.8 {d8}, [r4]! vld1.16 {d8}, [r4]! vld1.32 {d8}, [r4]! vld1.64 {d8}, [r4]! vld1.8 {d8}, [r4], r6 vld1.16 {d8}, [r4], r6 vld1.32 {d8}, [r4], r6 vld1.64 {d8}, [r4], r6 vld1.8 {d8, d9}, [r4]! vld1.16 {d8, d9}, [r4]! vld1.32 {d8, d9}, [r4]! vld1.64 {d8, d9}, [r4]! vld1.8 {d8, d9}, [r4], r6 vld1.16 {d8, d9}, [r4], r6 vld1.32 {d8, d9}, [r4], r6 vld1.64 {d8, d9}, [r4], r6 vld1.8 {d8, d9, d10}, [r4]! vld1.16 {d8, d9, d10}, [r4]! vld1.32 {d8, d9, d10}, [r4]! vld1.64 {d8, d9, d10}, [r4]! vld1.8 {d8, d9, d10}, [r4], r6 vld1.16 {d8, d9, d10}, [r4], r6 vld1.32 {d8, d9, d10}, [r4], r6 vld1.64 {d8, d9, d10}, [r4], r6 vld1.8 {d8, d9, d10, d11}, [r4]! vld1.16 {d8, d9, d10, d11}, [r4]! vld1.32 {d8, d9, d10, d11}, [r4]! vld1.64 {d8, d9, d10, d11}, [r4]! vld1.8 {d8, d9, d10, d11}, [r4], r6 vld1.16 {d8, d9, d10, d11}, [r4], r6 vld1.32 {d8, d9, d10, d11}, [r4], r6 vld1.64 {d8, d9, d10, d11}, [r4], r6 vld2.8 {d8, d9}, [r4]! vld2.16 {d8, d9}, [r4]! vld2.32 {d8, d9}, [r4]! vld2.8 {d8, d9}, [r4], r6 vld2.16 {d8, d9}, [r4], r6 vld2.32 {d8, d9}, [r4], r6 vld2.8 {d8, d10}, [r4]! vld2.16 {d8, d10}, [r4]! vld2.32 {d8, d10}, [r4]! vld2.8 {d8, d10}, [r4], r6 vld2.16 {d8, d10}, [r4], r6 vld2.32 {d8, d10}, [r4], r6 vld3.8 {d8, d9, d10}, [r4]! vld3.16 {d8, d9, d10}, [r4]! vld3.32 {d8, d9, d10}, [r4]! vld3.8 {d8, d10, d12}, [r4], r6 vld3.16 {d8, d10, d12}, [r4], r6 vld3.32 {d8, d10, d12}, [r4], r6 vld4.8 {d8, d9, d10, d11}, [r4]! vld4.16 {d8, d9, d10, d11}, [r4]! vld4.32 {d8, d9, d10, d11}, [r4]! vld4.8 {d8, d10, d12, d14}, [r4], r6 vld4.16 {d8, d10, d12, d14}, [r4], r6 vld4.32 {d8, d10, d12, d14}, [r4], r6 vld1.16 {d8, d9}, [r4] vld1.32 {d8, d9}, [r4] vld1.64 {d8, d9}, [r4] vld1.8 {d8, d9}, [r4] vld2.16 {d8, d9}, [r4] vld2.32 {d8, d9}, [r4] vld2.8 {d8, d9}, [r4] vld2.16 {d8, d9}, [r4]! vld2.16 {d8, d9}, [r4], r6 vld2.32 {d8, d9}, [r4]! vld2.32 {d8, d9}, [r4], r6 vld2.8 {d8, d9}, [r4]! vld2.8 {d8, d9}, [r4], r6 vld2.16 {d8, d10}, [r4] vld2.32 {d8, d10}, [r4] vld2.8 {d8, d10}, [r4] vld2.16 {d8, d9, d10, d11}, [r4]! vld2.16 {d8, d9, d10, d11}, [r4], r6 vld2.32 {d8, d9, d10, d11}, [r4]! vld2.32 {d8, d9, d10, d11}, [r4], r6 vld2.8 {d8, d9, d10, d11}, [r4]! vld2.8 {d8, d9, d10, d11}, [r4], r6 vld3.8 {d8, d9, d10}, [r4] vld3.16 {d8, d9, d10}, [r4] vld3.32 {d8, d9, d10}, [r4] vld4.8 {d8, d9, d10, d11}, [r4] vld4.16 {d8, d9, d10, d11}, [r4] vld4.32 {d8, d9, d10, d11}, [r4] vld3.8 {d8, d10, d12}, [r4] vld3.16 {d8, d10, d12}, [r4] vld3.32 {d8, d10, d12}, [r4] vld4.8 {d8, d10, d12, d14}, [r4] vld4.16 {d8, d10, d12, d14}, [r4] vld4.32 {d8, d10, d12, d14}, [r4] vld2.8 {d0[], d1[]}, [r2] vld2.16 {d0[], d1[]}, [r2] vld2.32 {d0[], d1[]}, [r2] vld2.8 {d0[], d1[]}, [r2]! vld2.16 {d0[], d1[]}, [r2]! vld2.32 {d0[], d1[]}, [r2]! vld2.8 {d0[], d1[]}, [r2], r3 vld2.16 {d0[], d1[]}, [r2], r3 vld2.32 {d0[], d1[]}, [r2], r3 vld2.8 {d0[], d2[]}, [r3] vld2.16 {d0[], d2[]}, [r3] vld2.32 {d0[], d2[]}, [r3] vld2.8 {d0[], d2[]}, [r3]! vld2.16 {d0[], d2[]}, [r3]! vld2.32 {d0[], d2[]}, [r3]! vld2.8 {d0[], d2[]}, [r3], r4 vld2.16 {d0[], d2[]}, [r3], r4 vld2.32 {d0[], d2[]}, [r3], r4 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 3 0.50 vabs.s8 d16, d16 # CHECK-NEXT: 1 3 0.50 vabs.s16 d16, d16 # CHECK-NEXT: 1 3 0.50 vabs.s32 d16, d16 # CHECK-NEXT: 1 3 0.50 vabs.f32 d16, d16 # CHECK-NEXT: 1 3 0.50 vabs.s8 q8, q8 # CHECK-NEXT: 1 3 0.50 vabs.s16 q8, q8 # CHECK-NEXT: 1 3 0.50 vabs.s32 q8, q8 # CHECK-NEXT: 1 3 0.50 vabs.f32 q8, q8 # CHECK-NEXT: 1 3 0.50 vqabs.s8 d16, d16 # CHECK-NEXT: 1 3 0.50 vqabs.s16 d16, d16 # CHECK-NEXT: 1 3 0.50 vqabs.s32 d16, d16 # CHECK-NEXT: 1 3 0.50 vqabs.s8 q8, q8 # CHECK-NEXT: 1 3 0.50 vqabs.s16 q8, q8 # CHECK-NEXT: 1 3 0.50 vqabs.s32 q8, q8 # CHECK-NEXT: 1 3 0.50 vabd.s8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vabd.s16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vabd.s32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vabd.u8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vabd.u16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vabd.u32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vabd.f32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vabd.s8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vabd.s16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vabd.s32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vabd.u8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vabd.u16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vabd.u32 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vabd.f32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vabdl.s8 q8, d16, d17 # CHECK-NEXT: 1 3 0.50 vabdl.s16 q8, d16, d17 # CHECK-NEXT: 1 3 0.50 vabdl.s32 q8, d16, d17 # CHECK-NEXT: 1 3 0.50 vabdl.u8 q8, d16, d17 # CHECK-NEXT: 1 3 0.50 vabdl.u16 q8, d16, d17 # CHECK-NEXT: 1 3 0.50 vabdl.u32 q8, d16, d17 # CHECK-NEXT: 1 4 1.00 vaba.s8 d16, d18, d17 # CHECK-NEXT: 1 4 1.00 vaba.s16 d16, d18, d17 # CHECK-NEXT: 1 4 1.00 vaba.s32 d16, d18, d17 # CHECK-NEXT: 1 4 1.00 vaba.u8 d16, d18, d17 # CHECK-NEXT: 1 4 1.00 vaba.u16 d16, d18, d17 # CHECK-NEXT: 1 4 1.00 vaba.u32 d16, d18, d17 # CHECK-NEXT: 1 5 1.00 vaba.s8 q9, q8, q10 # CHECK-NEXT: 1 5 1.00 vaba.s16 q9, q8, q10 # CHECK-NEXT: 1 5 1.00 vaba.s32 q9, q8, q10 # CHECK-NEXT: 1 5 1.00 vaba.u8 q9, q8, q10 # CHECK-NEXT: 1 5 1.00 vaba.u16 q9, q8, q10 # CHECK-NEXT: 1 5 1.00 vaba.u32 q9, q8, q10 # CHECK-NEXT: 1 4 1.00 vabal.s8 q8, d19, d18 # CHECK-NEXT: 1 4 1.00 vabal.s16 q8, d19, d18 # CHECK-NEXT: 1 4 1.00 vabal.s32 q8, d19, d18 # CHECK-NEXT: 1 4 1.00 vabal.u8 q8, d19, d18 # CHECK-NEXT: 1 4 1.00 vabal.u16 q8, d19, d18 # CHECK-NEXT: 1 4 1.00 vabal.u32 q8, d19, d18 # CHECK-NEXT: 1 3 0.50 vadd.i8 d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vadd.i16 d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vadd.i64 d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vadd.i32 d16, d17, d16 # CHECK-NEXT: 1 5 0.50 vadd.f32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vadd.f32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vaddl.s8 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vaddl.s16 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vaddl.s32 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vaddl.u8 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vaddl.u16 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vaddl.u32 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vaddw.s8 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vaddw.s16 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vaddw.s32 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vaddw.u8 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vaddw.u16 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vaddw.u32 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vhadd.s8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhadd.s16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhadd.s32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhadd.u8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhadd.u16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhadd.u32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhadd.s8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vhadd.s16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vhadd.s32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vhadd.u8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vhadd.u16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vhadd.u32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vrhadd.s8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vrhadd.s16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vrhadd.s32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vrhadd.u8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vrhadd.u16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vrhadd.u32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vrhadd.s8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vrhadd.s16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vrhadd.s32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vrhadd.u8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vrhadd.u16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vrhadd.u32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqadd.s8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqadd.s16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqadd.s32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqadd.s64 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqadd.u8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqadd.u16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqadd.u32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqadd.u64 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqadd.s8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqadd.s16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqadd.s32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqadd.s64 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqadd.u8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqadd.u16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqadd.u32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqadd.u64 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vaddhn.i16 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vaddhn.i32 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vaddhn.i64 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vraddhn.i16 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vraddhn.i32 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vraddhn.i64 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vcnt.8 d16, d16 # CHECK-NEXT: 1 3 0.50 vcnt.8 q8, q8 # CHECK-NEXT: 1 3 0.50 vclz.i8 d16, d16 # CHECK-NEXT: 1 3 0.50 vclz.i16 d16, d16 # CHECK-NEXT: 1 3 0.50 vclz.i32 d16, d16 # CHECK-NEXT: 1 3 0.50 vclz.i8 q8, q8 # CHECK-NEXT: 1 3 0.50 vclz.i16 q8, q8 # CHECK-NEXT: 1 3 0.50 vclz.i32 q8, q8 # CHECK-NEXT: 1 3 0.50 vcls.s8 d16, d16 # CHECK-NEXT: 1 3 0.50 vcls.s16 d16, d16 # CHECK-NEXT: 1 3 0.50 vcls.s32 d16, d16 # CHECK-NEXT: 1 3 0.50 vcls.s8 q8, q8 # CHECK-NEXT: 1 3 0.50 vcls.s16 q8, q8 # CHECK-NEXT: 1 3 0.50 vcls.s32 q8, q8 # CHECK-NEXT: 1 3 0.50 vand d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vand q8, q8, q9 # CHECK-NEXT: 1 3 0.50 veor d16, d17, d16 # CHECK-NEXT: 1 3 0.50 veor q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vorr d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vorr q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vorr.i32 d16, #0x1000000 # CHECK-NEXT: 1 3 0.50 vorr.i32 q8, #0x1000000 # CHECK-NEXT: 1 3 0.50 vorr.i32 q8, #0x0 # CHECK-NEXT: 1 3 0.50 vbic d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vbic q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vbic.i32 d16, #0xff000000 # CHECK-NEXT: 1 3 0.50 vbic.i32 q8, #0xff000000 # CHECK-NEXT: 1 3 0.50 vorn d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vorn q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vmvn d16, d16 # CHECK-NEXT: 1 3 0.50 vmvn q8, q8 # CHECK-NEXT: 1 3 0.50 U vbsl d18, d17, d16 # CHECK-NEXT: 1 3 0.50 U vbsl q8, q10, q9 # CHECK-NEXT: 1 3 0.50 U vbit d18, d17, d16 # CHECK-NEXT: 1 3 0.50 U vbit q8, q10, q9 # CHECK-NEXT: 1 3 0.50 U vbif d18, d17, d16 # CHECK-NEXT: 1 3 0.50 U vbif q8, q10, q9 # CHECK-NEXT: 1 3 0.50 vceq.i8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vceq.i16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vceq.i32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vceq.f32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vceq.i8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vceq.i16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vceq.i32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vceq.f32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcge.s8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcge.s16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcge.s32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcge.u8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcge.u16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcge.u32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcge.f32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcge.s8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcge.s16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcge.s32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcge.u8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcge.u16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcge.u32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcge.f32 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vacge.f32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vacge.f32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcgt.s8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcgt.s16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcgt.s32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcgt.u8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcgt.u16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcgt.u32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcgt.f32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vcgt.s8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcgt.s16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcgt.s32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcgt.u8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcgt.u16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcgt.u32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vcgt.f32 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vacgt.f32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vacgt.f32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vtst.8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vtst.16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vtst.32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vtst.8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vtst.16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vtst.32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vceq.i8 d16, d16, #0 # CHECK-NEXT: 1 3 0.50 vcge.s8 d16, d16, #0 # CHECK-NEXT: 1 3 0.50 vcle.s8 d16, d16, #0 # CHECK-NEXT: 1 3 0.50 vcgt.s8 d16, d16, #0 # CHECK-NEXT: 1 3 0.50 vclt.s8 d16, d16, #0 # CHECK-NEXT: 1 5 0.50 vcvt.s32.f32 d16, d16 # CHECK-NEXT: 1 5 0.50 vcvt.u32.f32 d16, d16 # CHECK-NEXT: 1 5 0.50 vcvt.f32.s32 d16, d16 # CHECK-NEXT: 1 5 0.50 vcvt.f32.u32 d16, d16 # CHECK-NEXT: 1 5 0.50 vcvt.s32.f32 q8, q8 # CHECK-NEXT: 1 5 0.50 vcvt.u32.f32 q8, q8 # CHECK-NEXT: 1 5 0.50 vcvt.f32.s32 q8, q8 # CHECK-NEXT: 1 5 0.50 vcvt.f32.u32 q8, q8 # CHECK-NEXT: 1 5 0.50 vcvt.s32.f32 d16, d16, #1 # CHECK-NEXT: 1 5 0.50 vcvt.u32.f32 d16, d16, #1 # CHECK-NEXT: 1 5 0.50 vcvt.f32.s32 d16, d16, #1 # CHECK-NEXT: 1 5 0.50 vcvt.f32.u32 d16, d16, #1 # CHECK-NEXT: 1 5 0.50 vcvt.s32.f32 q8, q8, #1 # CHECK-NEXT: 1 5 0.50 vcvt.u32.f32 q8, q8, #1 # CHECK-NEXT: 1 5 0.50 vcvt.f32.s32 q8, q8, #1 # CHECK-NEXT: 1 5 0.50 vcvt.f32.u32 q8, q8, #1 # CHECK-NEXT: 1 8 0.50 vcvt.f32.f16 q8, d16 # CHECK-NEXT: 1 8 0.50 vcvt.f16.f32 d16, q8 # CHECK-NEXT: 2 8 1.00 vdup.8 d16, r0 # CHECK-NEXT: 2 8 1.00 vdup.16 d16, r0 # CHECK-NEXT: 2 8 1.00 vdup.32 d16, r0 # CHECK-NEXT: 2 8 1.00 vdup.8 q8, r0 # CHECK-NEXT: 2 8 1.00 vdup.16 q8, r0 # CHECK-NEXT: 2 8 1.00 vdup.32 q8, r0 # CHECK-NEXT: 1 3 0.50 vdup.8 d16, d16[1] # CHECK-NEXT: 1 3 0.50 vdup.16 d16, d16[1] # CHECK-NEXT: 1 3 0.50 vdup.32 d16, d16[1] # CHECK-NEXT: 1 3 0.50 vdup.8 q8, d16[1] # CHECK-NEXT: 1 3 0.50 vdup.16 q8, d16[1] # CHECK-NEXT: 1 3 0.50 vdup.32 q8, d16[1] # CHECK-NEXT: 1 5 0.50 vmin.s8 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmin.s16 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmin.s32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmin.u8 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmin.u16 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmin.u32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmin.f32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmin.s8 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmin.s16 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmin.s32 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmin.u8 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmin.u16 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmin.u32 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmin.f32 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmax.s8 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmax.s16 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmax.s32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmax.u8 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmax.u16 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmax.u32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmax.f32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmax.s8 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmax.s16 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmax.s32 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmax.u8 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmax.u16 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmax.u32 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmax.f32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vmov.i8 d16, #0x8 # CHECK-NEXT: 1 3 0.50 vmov.i16 d16, #0x10 # CHECK-NEXT: 1 3 0.50 vmov.i16 d16, #0x1000 # CHECK-NEXT: 1 3 0.50 vmov.i32 d16, #0x20 # CHECK-NEXT: 1 3 0.50 vmov.i32 d16, #0x2000 # CHECK-NEXT: 1 3 0.50 vmov.i32 d16, #0x200000 # CHECK-NEXT: 1 3 0.50 vmov.i32 d16, #0x20000000 # CHECK-NEXT: 1 3 0.50 vmov.i32 d16, #0x20ff # CHECK-NEXT: 1 3 0.50 vmov.i32 d16, #0x20ffff # CHECK-NEXT: 1 3 0.50 vmov.i64 d16, #0xff0000ff0000ffff # CHECK-NEXT: 1 3 0.50 vmov.i8 q8, #0x8 # CHECK-NEXT: 1 3 0.50 vmov.i16 q8, #0x10 # CHECK-NEXT: 1 3 0.50 vmov.i16 q8, #0x1000 # CHECK-NEXT: 1 3 0.50 vmov.i32 q8, #0x20 # CHECK-NEXT: 1 3 0.50 vmov.i32 q8, #0x2000 # CHECK-NEXT: 1 3 0.50 vmov.i32 q8, #0x200000 # CHECK-NEXT: 1 3 0.50 vmov.i32 q8, #0x20000000 # CHECK-NEXT: 1 3 0.50 vmov.i32 q8, #0x20ff # CHECK-NEXT: 1 3 0.50 vmov.i32 q8, #0x20ffff # CHECK-NEXT: 1 3 0.50 vmov.i64 q8, #0xff0000ff0000ffff # CHECK-NEXT: 1 3 0.50 vmvn.i16 d16, #0x10 # CHECK-NEXT: 1 3 0.50 vmvn.i16 d16, #0x1000 # CHECK-NEXT: 1 3 0.50 vmvn.i32 d16, #0x20 # CHECK-NEXT: 1 3 0.50 vmvn.i32 d16, #0x2000 # CHECK-NEXT: 1 3 0.50 vmvn.i32 d16, #0x200000 # CHECK-NEXT: 1 3 0.50 vmvn.i32 d16, #0x20000000 # CHECK-NEXT: 1 3 0.50 vmvn.i32 d16, #0x20ff # CHECK-NEXT: 1 3 0.50 vmvn.i32 d16, #0x20ffff # CHECK-NEXT: 1 3 1.00 vmovl.s8 q8, d16 # CHECK-NEXT: 1 3 1.00 vmovl.s16 q8, d16 # CHECK-NEXT: 1 3 1.00 vmovl.s32 q8, d16 # CHECK-NEXT: 1 3 1.00 vmovl.u8 q8, d16 # CHECK-NEXT: 1 3 1.00 vmovl.u16 q8, d16 # CHECK-NEXT: 1 3 1.00 vmovl.u32 q8, d16 # CHECK-NEXT: 1 3 0.50 vmovn.i16 d16, q8 # CHECK-NEXT: 1 3 0.50 vmovn.i32 d16, q8 # CHECK-NEXT: 1 3 0.50 vmovn.i64 d16, q8 # CHECK-NEXT: 1 4 1.00 vqmovn.s16 d16, q8 # CHECK-NEXT: 1 4 1.00 vqmovn.s32 d16, q8 # CHECK-NEXT: 1 4 1.00 vqmovn.s64 d16, q8 # CHECK-NEXT: 1 4 1.00 vqmovn.u16 d16, q8 # CHECK-NEXT: 1 4 1.00 vqmovn.u32 d16, q8 # CHECK-NEXT: 1 4 1.00 vqmovn.u64 d16, q8 # CHECK-NEXT: 1 4 1.00 vqmovun.s16 d16, q8 # CHECK-NEXT: 1 4 1.00 vqmovun.s32 d16, q8 # CHECK-NEXT: 1 4 1.00 vqmovun.s64 d16, q8 # CHECK-NEXT: 2 6 1.00 vmov.s8 r0, d16[1] # CHECK-NEXT: 2 6 1.00 vmov.s16 r0, d16[1] # CHECK-NEXT: 2 6 1.00 vmov.u8 r0, d16[1] # CHECK-NEXT: 2 6 1.00 vmov.u16 r0, d16[1] # CHECK-NEXT: 2 6 1.00 vmov.32 r0, d16[1] # CHECK-NEXT: 2 8 1.00 vmov.8 d16[1], r1 # CHECK-NEXT: 2 8 1.00 vmov.16 d16[1], r1 # CHECK-NEXT: 2 8 1.00 vmov.32 d16[1], r1 # CHECK-NEXT: 2 8 1.00 vmov.8 d18[1], r1 # CHECK-NEXT: 2 8 1.00 vmov.16 d18[1], r1 # CHECK-NEXT: 2 8 1.00 vmov.32 d18[1], r1 # CHECK-NEXT: 1 5 1.00 vmla.i8 d16, d18, d17 # CHECK-NEXT: 1 5 1.00 vmla.i16 d16, d18, d17 # CHECK-NEXT: 1 5 1.00 vmla.i32 d16, d18, d17 # CHECK-NEXT: 1 9 0.50 vmla.f32 d16, d18, d17 # CHECK-NEXT: 1 6 1.00 vmla.i8 q9, q8, q10 # CHECK-NEXT: 1 6 1.00 vmla.i16 q9, q8, q10 # CHECK-NEXT: 1 6 1.00 vmla.i32 q9, q8, q10 # CHECK-NEXT: 1 9 0.50 vmla.f32 q9, q8, q10 # CHECK-NEXT: 1 5 1.00 vmlal.s8 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmlal.s16 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmlal.s32 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmlal.u8 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmlal.u16 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmlal.u32 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vqdmlal.s16 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vqdmlal.s32 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmls.i8 d16, d18, d17 # CHECK-NEXT: 1 5 1.00 vmls.i16 d16, d18, d17 # CHECK-NEXT: 1 5 1.00 vmls.i32 d16, d18, d17 # CHECK-NEXT: 1 9 0.50 vmls.f32 d16, d18, d17 # CHECK-NEXT: 1 6 1.00 vmls.i8 q9, q8, q10 # CHECK-NEXT: 1 6 1.00 vmls.i16 q9, q8, q10 # CHECK-NEXT: 1 6 1.00 vmls.i32 q9, q8, q10 # CHECK-NEXT: 1 9 0.50 vmls.f32 q9, q8, q10 # CHECK-NEXT: 1 5 1.00 vmlsl.s8 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmlsl.s16 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmlsl.s32 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmlsl.u8 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmlsl.u16 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmlsl.u32 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vqdmlsl.s16 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vqdmlsl.s32 q8, d19, d18 # CHECK-NEXT: 1 5 1.00 vmul.i8 d16, d16, d17 # CHECK-NEXT: 1 5 1.00 vmul.i16 d16, d16, d17 # CHECK-NEXT: 1 5 1.00 vmul.i32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vmul.f32 d16, d16, d17 # CHECK-NEXT: 1 6 1.00 vmul.i8 q8, q8, q9 # CHECK-NEXT: 1 6 1.00 vmul.i16 q8, q8, q9 # CHECK-NEXT: 1 6 1.00 vmul.i32 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vmul.f32 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vmul.p8 d16, d16, d17 # CHECK-NEXT: 1 6 1.00 vmul.p8 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqdmulh.s16 d16, d16, d17 # CHECK-NEXT: 1 5 1.00 vqdmulh.s32 d16, d16, d17 # CHECK-NEXT: 1 6 1.00 vqdmulh.s16 q8, q8, q9 # CHECK-NEXT: 1 6 1.00 vqdmulh.s32 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqrdmulh.s16 d16, d16, d17 # CHECK-NEXT: 1 5 1.00 vqrdmulh.s32 d16, d16, d17 # CHECK-NEXT: 1 6 1.00 vqrdmulh.s16 q8, q8, q9 # CHECK-NEXT: 1 6 1.00 vqrdmulh.s32 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vmull.s8 q8, d16, d17 # CHECK-NEXT: 1 5 1.00 vmull.s16 q8, d16, d17 # CHECK-NEXT: 1 5 1.00 vmull.s32 q8, d16, d17 # CHECK-NEXT: 1 5 1.00 vmull.u8 q8, d16, d17 # CHECK-NEXT: 1 5 1.00 vmull.u16 q8, d16, d17 # CHECK-NEXT: 1 5 1.00 vmull.u32 q8, d16, d17 # CHECK-NEXT: 1 5 1.00 vmull.p8 q8, d16, d17 # CHECK-NEXT: 1 5 1.00 vqdmull.s16 q8, d16, d17 # CHECK-NEXT: 1 5 1.00 vqdmull.s32 q8, d16, d17 # CHECK-NEXT: 1 3 0.50 vneg.s8 d16, d16 # CHECK-NEXT: 1 3 0.50 vneg.s16 d16, d16 # CHECK-NEXT: 1 3 0.50 vneg.s32 d16, d16 # CHECK-NEXT: 1 3 0.50 vneg.f32 d16, d16 # CHECK-NEXT: 1 3 0.50 vneg.s8 q8, q8 # CHECK-NEXT: 1 3 0.50 vneg.s16 q8, q8 # CHECK-NEXT: 1 3 0.50 vneg.s32 q8, q8 # CHECK-NEXT: 1 3 0.50 vneg.f32 q8, q8 # CHECK-NEXT: 1 3 0.50 vqneg.s8 d16, d16 # CHECK-NEXT: 1 3 0.50 vqneg.s16 d16, d16 # CHECK-NEXT: 1 3 0.50 vqneg.s32 d16, d16 # CHECK-NEXT: 1 3 0.50 vqneg.s8 q8, q8 # CHECK-NEXT: 1 3 0.50 vqneg.s16 q8, q8 # CHECK-NEXT: 1 3 0.50 vqneg.s32 q8, q8 # CHECK-NEXT: 1 3 0.50 vpadd.i8 d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vpadd.i16 d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vpadd.i32 d16, d17, d16 # CHECK-NEXT: 1 5 0.50 vpadd.f32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpaddl.s8 d16, d16 # CHECK-NEXT: 1 3 0.50 vpaddl.s16 d16, d16 # CHECK-NEXT: 1 3 0.50 vpaddl.s32 d16, d16 # CHECK-NEXT: 1 3 0.50 vpaddl.u8 d16, d16 # CHECK-NEXT: 1 3 0.50 vpaddl.u16 d16, d16 # CHECK-NEXT: 1 3 0.50 vpaddl.u32 d16, d16 # CHECK-NEXT: 1 3 0.50 vpaddl.s8 q8, q8 # CHECK-NEXT: 1 3 0.50 vpaddl.s16 q8, q8 # CHECK-NEXT: 1 3 0.50 vpaddl.s32 q8, q8 # CHECK-NEXT: 1 3 0.50 vpaddl.u8 q8, q8 # CHECK-NEXT: 1 3 0.50 vpaddl.u16 q8, q8 # CHECK-NEXT: 1 3 0.50 vpaddl.u32 q8, q8 # CHECK-NEXT: 1 4 1.00 vpadal.s8 d16, d17 # CHECK-NEXT: 1 4 1.00 vpadal.s16 d16, d17 # CHECK-NEXT: 1 4 1.00 vpadal.s32 d16, d17 # CHECK-NEXT: 1 4 1.00 vpadal.u8 d16, d17 # CHECK-NEXT: 1 4 1.00 vpadal.u16 d16, d17 # CHECK-NEXT: 1 4 1.00 vpadal.u32 d16, d17 # CHECK-NEXT: 1 4 1.00 vpadal.s8 q9, q8 # CHECK-NEXT: 1 4 1.00 vpadal.s16 q9, q8 # CHECK-NEXT: 1 4 1.00 vpadal.s32 q9, q8 # CHECK-NEXT: 1 4 1.00 vpadal.u8 q9, q8 # CHECK-NEXT: 1 4 1.00 vpadal.u16 q9, q8 # CHECK-NEXT: 1 4 1.00 vpadal.u32 q9, q8 # CHECK-NEXT: 1 3 0.50 vpmin.s8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpmin.s16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpmin.s32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpmin.u8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpmin.u16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpmin.u32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vpmin.f32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpmax.s8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpmax.s16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpmax.s32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpmax.u8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpmax.u16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vpmax.u32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vpmax.f32 d16, d16, d17 # CHECK-NEXT: 1 5 0.50 vrecpe.u32 d16, d16 # CHECK-NEXT: 1 5 0.50 vrecpe.u32 q8, q8 # CHECK-NEXT: 1 5 0.50 vrecpe.f32 d16, d16 # CHECK-NEXT: 1 5 0.50 vrecpe.f32 q8, q8 # CHECK-NEXT: 1 9 0.50 vrecps.f32 d16, d16, d17 # CHECK-NEXT: 1 9 0.50 vrecps.f32 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vrsqrte.u32 d16, d16 # CHECK-NEXT: 1 5 0.50 vrsqrte.u32 q8, q8 # CHECK-NEXT: 1 5 0.50 vrsqrte.f32 d16, d16 # CHECK-NEXT: 1 5 0.50 vrsqrte.f32 q8, q8 # CHECK-NEXT: 1 9 0.50 vrsqrts.f32 d16, d16, d17 # CHECK-NEXT: 1 9 0.50 vrsqrts.f32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vrev64.8 d16, d16 # CHECK-NEXT: 1 3 0.50 vrev64.16 d16, d16 # CHECK-NEXT: 1 3 0.50 vrev64.32 d16, d16 # CHECK-NEXT: 1 3 0.50 vrev64.8 q8, q8 # CHECK-NEXT: 1 3 0.50 vrev64.16 q8, q8 # CHECK-NEXT: 1 3 0.50 vrev64.32 q8, q8 # CHECK-NEXT: 1 3 0.50 vrev32.8 d16, d16 # CHECK-NEXT: 1 3 0.50 vrev32.16 d16, d16 # CHECK-NEXT: 1 3 0.50 vrev32.8 q8, q8 # CHECK-NEXT: 1 3 0.50 vrev32.16 q8, q8 # CHECK-NEXT: 1 3 0.50 vrev16.8 d16, d16 # CHECK-NEXT: 1 3 0.50 vrev16.8 q8, q8 # CHECK-NEXT: 1 4 1.00 vqshl.s8 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqshl.s16 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqshl.s32 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqshl.s64 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqshl.u8 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqshl.u16 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqshl.u32 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqshl.u64 d16, d16, d17 # CHECK-NEXT: 1 5 1.00 vqshl.s8 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqshl.s16 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqshl.s32 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqshl.s64 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqshl.u8 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqshl.u16 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqshl.u32 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqshl.u64 q8, q8, q9 # CHECK-NEXT: 1 4 1.00 vqshl.s8 d16, d16, #7 # CHECK-NEXT: 1 4 1.00 vqshl.s16 d16, d16, #15 # CHECK-NEXT: 1 4 1.00 vqshl.s32 d16, d16, #31 # CHECK-NEXT: 1 4 1.00 vqshl.s64 d16, d16, #63 # CHECK-NEXT: 1 4 1.00 vqshl.u8 d16, d16, #7 # CHECK-NEXT: 1 4 1.00 vqshl.u16 d16, d16, #15 # CHECK-NEXT: 1 4 1.00 vqshl.u32 d16, d16, #31 # CHECK-NEXT: 1 4 1.00 vqshl.u64 d16, d16, #63 # CHECK-NEXT: 1 4 1.00 vqshlu.s8 d16, d16, #7 # CHECK-NEXT: 1 4 1.00 vqshlu.s16 d16, d16, #15 # CHECK-NEXT: 1 4 1.00 vqshlu.s32 d16, d16, #31 # CHECK-NEXT: 1 4 1.00 vqshlu.s64 d16, d16, #63 # CHECK-NEXT: 1 4 1.00 vqshl.s8 q8, q8, #7 # CHECK-NEXT: 1 4 1.00 vqshl.s16 q8, q8, #15 # CHECK-NEXT: 1 4 1.00 vqshl.s32 q8, q8, #31 # CHECK-NEXT: 1 4 1.00 vqshl.s64 q8, q8, #63 # CHECK-NEXT: 1 4 1.00 vqshl.u8 q8, q8, #7 # CHECK-NEXT: 1 4 1.00 vqshl.u16 q8, q8, #15 # CHECK-NEXT: 1 4 1.00 vqshl.u32 q8, q8, #31 # CHECK-NEXT: 1 4 1.00 vqshl.u64 q8, q8, #63 # CHECK-NEXT: 1 4 1.00 vqshlu.s8 q8, q8, #7 # CHECK-NEXT: 1 4 1.00 vqshlu.s16 q8, q8, #15 # CHECK-NEXT: 1 4 1.00 vqshlu.s32 q8, q8, #31 # CHECK-NEXT: 1 4 1.00 vqshlu.s64 q8, q8, #63 # CHECK-NEXT: 1 4 1.00 vqrshl.s8 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqrshl.s16 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqrshl.s32 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqrshl.s64 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqrshl.u8 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqrshl.u16 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqrshl.u32 d16, d16, d17 # CHECK-NEXT: 1 4 1.00 vqrshl.u64 d16, d16, d17 # CHECK-NEXT: 1 5 1.00 vqrshl.s8 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqrshl.s16 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqrshl.s32 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqrshl.s64 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqrshl.u8 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqrshl.u16 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqrshl.u32 q8, q8, q9 # CHECK-NEXT: 1 5 1.00 vqrshl.u64 q8, q8, q9 # CHECK-NEXT: 1 4 1.00 vqshrn.s16 d16, q8, #8 # CHECK-NEXT: 1 4 1.00 vqshrn.s32 d16, q8, #16 # CHECK-NEXT: 1 4 1.00 vqshrn.s64 d16, q8, #32 # CHECK-NEXT: 1 4 1.00 vqshrn.u16 d16, q8, #8 # CHECK-NEXT: 1 4 1.00 vqshrn.u32 d16, q8, #16 # CHECK-NEXT: 1 4 1.00 vqshrn.u64 d16, q8, #32 # CHECK-NEXT: 1 4 1.00 vqshrun.s16 d16, q8, #8 # CHECK-NEXT: 1 4 1.00 vqshrun.s32 d16, q8, #16 # CHECK-NEXT: 1 4 1.00 vqshrun.s64 d16, q8, #32 # CHECK-NEXT: 1 4 1.00 vqrshrn.s16 d16, q8, #8 # CHECK-NEXT: 1 4 1.00 vqrshrn.s32 d16, q8, #16 # CHECK-NEXT: 1 4 1.00 vqrshrn.s64 d16, q8, #32 # CHECK-NEXT: 1 4 1.00 vqrshrn.u16 d16, q8, #8 # CHECK-NEXT: 1 4 1.00 vqrshrn.u32 d16, q8, #16 # CHECK-NEXT: 1 4 1.00 vqrshrn.u64 d16, q8, #32 # CHECK-NEXT: 1 4 1.00 vqrshrun.s16 d16, q8, #8 # CHECK-NEXT: 1 4 1.00 vqrshrun.s32 d16, q8, #16 # CHECK-NEXT: 1 4 1.00 vqrshrun.s64 d16, q8, #32 # CHECK-NEXT: 1 3 1.00 vshl.u8 d16, d17, d16 # CHECK-NEXT: 1 3 1.00 vshl.u16 d16, d17, d16 # CHECK-NEXT: 1 3 1.00 vshl.u32 d16, d17, d16 # CHECK-NEXT: 1 3 1.00 vshl.u64 d16, d17, d16 # CHECK-NEXT: 1 3 1.00 vshl.i8 d16, d16, #7 # CHECK-NEXT: 1 3 1.00 vshl.i16 d16, d16, #15 # CHECK-NEXT: 1 3 1.00 vshl.i32 d16, d16, #31 # CHECK-NEXT: 1 3 1.00 vshl.i64 d16, d16, #63 # CHECK-NEXT: 1 4 1.00 vshl.u8 q8, q9, q8 # CHECK-NEXT: 1 4 1.00 vshl.u16 q8, q9, q8 # CHECK-NEXT: 1 4 1.00 vshl.u32 q8, q9, q8 # CHECK-NEXT: 1 4 1.00 vshl.u64 q8, q9, q8 # CHECK-NEXT: 1 3 1.00 vshl.i8 q8, q8, #7 # CHECK-NEXT: 1 3 1.00 vshl.i16 q8, q8, #15 # CHECK-NEXT: 1 3 1.00 vshl.i32 q8, q8, #31 # CHECK-NEXT: 1 3 1.00 vshl.i64 q8, q8, #63 # CHECK-NEXT: 1 3 1.00 vshr.u8 d16, d16, #7 # CHECK-NEXT: 1 3 1.00 vshr.u16 d16, d16, #15 # CHECK-NEXT: 1 3 1.00 vshr.u32 d16, d16, #31 # CHECK-NEXT: 1 3 1.00 vshr.u64 d16, d16, #63 # CHECK-NEXT: 1 3 1.00 vshr.u8 q8, q8, #7 # CHECK-NEXT: 1 3 1.00 vshr.u16 q8, q8, #15 # CHECK-NEXT: 1 3 1.00 vshr.u32 q8, q8, #31 # CHECK-NEXT: 1 3 1.00 vshr.u64 q8, q8, #63 # CHECK-NEXT: 1 3 1.00 vshr.s8 d16, d16, #7 # CHECK-NEXT: 1 3 1.00 vshr.s16 d16, d16, #15 # CHECK-NEXT: 1 3 1.00 vshr.s32 d16, d16, #31 # CHECK-NEXT: 1 3 1.00 vshr.s64 d16, d16, #63 # CHECK-NEXT: 1 3 1.00 vshr.s8 q8, q8, #7 # CHECK-NEXT: 1 3 1.00 vshr.s16 q8, q8, #15 # CHECK-NEXT: 1 3 1.00 vshr.s32 q8, q8, #31 # CHECK-NEXT: 1 3 1.00 vshr.s64 q8, q8, #63 # CHECK-NEXT: 1 4 1.00 vsra.u8 d16, d16, #7 # CHECK-NEXT: 1 4 1.00 vsra.u16 d16, d16, #15 # CHECK-NEXT: 1 4 1.00 vsra.u32 d16, d16, #31 # CHECK-NEXT: 1 4 1.00 vsra.u64 d16, d16, #63 # CHECK-NEXT: 1 4 1.00 vsra.u8 q8, q8, #7 # CHECK-NEXT: 1 4 1.00 vsra.u16 q8, q8, #15 # CHECK-NEXT: 1 4 1.00 vsra.u32 q8, q8, #31 # CHECK-NEXT: 1 4 1.00 vsra.u64 q8, q8, #63 # CHECK-NEXT: 1 4 1.00 vsra.s8 d16, d16, #7 # CHECK-NEXT: 1 4 1.00 vsra.s16 d16, d16, #15 # CHECK-NEXT: 1 4 1.00 vsra.s32 d16, d16, #31 # CHECK-NEXT: 1 4 1.00 vsra.s64 d16, d16, #63 # CHECK-NEXT: 1 4 1.00 vsra.s8 q8, q8, #7 # CHECK-NEXT: 1 4 1.00 vsra.s16 q8, q8, #15 # CHECK-NEXT: 1 4 1.00 vsra.s32 q8, q8, #31 # CHECK-NEXT: 1 4 1.00 vsra.s64 q8, q8, #63 # CHECK-NEXT: 1 4 1.00 vsri.8 d16, d16, #7 # CHECK-NEXT: 1 4 1.00 vsri.16 d16, d16, #15 # CHECK-NEXT: 1 4 1.00 vsri.32 d16, d16, #31 # CHECK-NEXT: 1 4 1.00 vsri.64 d16, d16, #63 # CHECK-NEXT: 1 5 1.00 vsri.8 q8, q8, #7 # CHECK-NEXT: 1 5 1.00 vsri.16 q8, q8, #15 # CHECK-NEXT: 1 5 1.00 vsri.32 q8, q8, #31 # CHECK-NEXT: 1 5 1.00 vsri.64 q8, q8, #63 # CHECK-NEXT: 1 4 1.00 vsli.8 d16, d16, #7 # CHECK-NEXT: 1 4 1.00 vsli.16 d16, d16, #15 # CHECK-NEXT: 1 4 1.00 vsli.32 d16, d16, #31 # CHECK-NEXT: 1 4 1.00 vsli.64 d16, d16, #63 # CHECK-NEXT: 1 5 1.00 vsli.8 q8, q8, #7 # CHECK-NEXT: 1 5 1.00 vsli.16 q8, q8, #15 # CHECK-NEXT: 1 5 1.00 vsli.32 q8, q8, #31 # CHECK-NEXT: 1 5 1.00 vsli.64 q8, q8, #63 # CHECK-NEXT: 1 3 1.00 vshll.s8 q8, d16, #7 # CHECK-NEXT: 1 3 1.00 vshll.s16 q8, d16, #15 # CHECK-NEXT: 1 3 1.00 vshll.s32 q8, d16, #31 # CHECK-NEXT: 1 3 1.00 vshll.u8 q8, d16, #7 # CHECK-NEXT: 1 3 1.00 vshll.u16 q8, d16, #15 # CHECK-NEXT: 1 3 1.00 vshll.u32 q8, d16, #31 # CHECK-NEXT: 1 3 1.00 vshll.i8 q8, d16, #8 # CHECK-NEXT: 1 3 1.00 vshll.i16 q8, d16, #16 # CHECK-NEXT: 1 3 1.00 vshll.i32 q8, d16, #32 # CHECK-NEXT: 1 3 1.00 vshrn.i16 d16, q8, #8 # CHECK-NEXT: 1 3 1.00 vshrn.i32 d16, q8, #16 # CHECK-NEXT: 1 3 1.00 vshrn.i64 d16, q8, #32 # CHECK-NEXT: 1 4 1.00 vrshl.s8 d16, d17, d16 # CHECK-NEXT: 1 4 1.00 vrshl.s16 d16, d17, d16 # CHECK-NEXT: 1 4 1.00 vrshl.s32 d16, d17, d16 # CHECK-NEXT: 1 4 1.00 vrshl.s64 d16, d17, d16 # CHECK-NEXT: 1 4 1.00 vrshl.u8 d16, d17, d16 # CHECK-NEXT: 1 4 1.00 vrshl.u16 d16, d17, d16 # CHECK-NEXT: 1 4 1.00 vrshl.u32 d16, d17, d16 # CHECK-NEXT: 1 4 1.00 vrshl.u64 d16, d17, d16 # CHECK-NEXT: 1 5 1.00 vrshl.s8 q8, q9, q8 # CHECK-NEXT: 1 5 1.00 vrshl.s16 q8, q9, q8 # CHECK-NEXT: 1 5 1.00 vrshl.s32 q8, q9, q8 # CHECK-NEXT: 1 5 1.00 vrshl.s64 q8, q9, q8 # CHECK-NEXT: 1 5 1.00 vrshl.u8 q8, q9, q8 # CHECK-NEXT: 1 5 1.00 vrshl.u16 q8, q9, q8 # CHECK-NEXT: 1 5 1.00 vrshl.u32 q8, q9, q8 # CHECK-NEXT: 1 5 1.00 vrshl.u64 q8, q9, q8 # CHECK-NEXT: 1 4 1.00 vrshr.s8 d16, d16, #8 # CHECK-NEXT: 1 4 1.00 vrshr.s16 d16, d16, #16 # CHECK-NEXT: 1 4 1.00 vrshr.s32 d16, d16, #32 # CHECK-NEXT: 1 4 1.00 vrshr.s64 d16, d16, #64 # CHECK-NEXT: 1 4 1.00 vrshr.u8 d16, d16, #8 # CHECK-NEXT: 1 4 1.00 vrshr.u16 d16, d16, #16 # CHECK-NEXT: 1 4 1.00 vrshr.u32 d16, d16, #32 # CHECK-NEXT: 1 4 1.00 vrshr.u64 d16, d16, #64 # CHECK-NEXT: 1 4 1.00 vrshr.s8 q8, q8, #8 # CHECK-NEXT: 1 4 1.00 vrshr.s16 q8, q8, #16 # CHECK-NEXT: 1 4 1.00 vrshr.s32 q8, q8, #32 # CHECK-NEXT: 1 4 1.00 vrshr.s64 q8, q8, #64 # CHECK-NEXT: 1 4 1.00 vrshr.u8 q8, q8, #8 # CHECK-NEXT: 1 4 1.00 vrshr.u16 q8, q8, #16 # CHECK-NEXT: 1 4 1.00 vrshr.u32 q8, q8, #32 # CHECK-NEXT: 1 4 1.00 vrshr.u64 q8, q8, #64 # CHECK-NEXT: 1 4 1.00 vrshrn.i16 d16, q8, #8 # CHECK-NEXT: 1 4 1.00 vrshrn.i32 d16, q8, #16 # CHECK-NEXT: 1 4 1.00 vrshrn.i64 d16, q8, #32 # CHECK-NEXT: 1 4 1.00 vqrshrn.s16 d16, q8, #4 # CHECK-NEXT: 1 4 1.00 vqrshrn.s32 d16, q8, #13 # CHECK-NEXT: 1 4 1.00 vqrshrn.s64 d16, q8, #13 # CHECK-NEXT: 1 4 1.00 vqrshrn.u16 d16, q8, #4 # CHECK-NEXT: 1 4 1.00 vqrshrn.u32 d16, q8, #13 # CHECK-NEXT: 1 4 1.00 vqrshrn.u64 d16, q8, #13 # CHECK-NEXT: 1 4 1.00 vsra.s8 d17, d16, #8 # CHECK-NEXT: 1 4 1.00 vsra.s16 d17, d16, #16 # CHECK-NEXT: 1 4 1.00 vsra.s32 d17, d16, #32 # CHECK-NEXT: 1 4 1.00 vsra.s64 d17, d16, #64 # CHECK-NEXT: 1 4 1.00 vsra.s8 q8, q9, #8 # CHECK-NEXT: 1 4 1.00 vsra.s16 q8, q9, #16 # CHECK-NEXT: 1 4 1.00 vsra.s32 q8, q9, #32 # CHECK-NEXT: 1 4 1.00 vsra.s64 q8, q9, #64 # CHECK-NEXT: 1 4 1.00 vsra.u8 d17, d16, #8 # CHECK-NEXT: 1 4 1.00 vsra.u16 d17, d16, #16 # CHECK-NEXT: 1 4 1.00 vsra.u32 d17, d16, #32 # CHECK-NEXT: 1 4 1.00 vsra.u64 d17, d16, #64 # CHECK-NEXT: 1 4 1.00 vsra.u8 q8, q9, #8 # CHECK-NEXT: 1 4 1.00 vsra.u16 q8, q9, #16 # CHECK-NEXT: 1 4 1.00 vsra.u32 q8, q9, #32 # CHECK-NEXT: 1 4 1.00 vsra.u64 q8, q9, #64 # CHECK-NEXT: 1 4 1.00 vrsra.s8 d17, d16, #8 # CHECK-NEXT: 1 4 1.00 vrsra.s16 d17, d16, #16 # CHECK-NEXT: 1 4 1.00 vrsra.s32 d17, d16, #32 # CHECK-NEXT: 1 4 1.00 vrsra.s64 d17, d16, #64 # CHECK-NEXT: 1 4 1.00 vrsra.u8 d17, d16, #8 # CHECK-NEXT: 1 4 1.00 vrsra.u16 d17, d16, #16 # CHECK-NEXT: 1 4 1.00 vrsra.u32 d17, d16, #32 # CHECK-NEXT: 1 4 1.00 vrsra.u64 d17, d16, #64 # CHECK-NEXT: 1 4 1.00 vrsra.s8 q8, q9, #8 # CHECK-NEXT: 1 4 1.00 vrsra.s16 q8, q9, #16 # CHECK-NEXT: 1 4 1.00 vrsra.s32 q8, q9, #32 # CHECK-NEXT: 1 4 1.00 vrsra.s64 q8, q9, #64 # CHECK-NEXT: 1 4 1.00 vrsra.u8 q8, q9, #8 # CHECK-NEXT: 1 4 1.00 vrsra.u16 q8, q9, #16 # CHECK-NEXT: 1 4 1.00 vrsra.u32 q8, q9, #32 # CHECK-NEXT: 1 4 1.00 vrsra.u64 q8, q9, #64 # CHECK-NEXT: 1 4 1.00 vsli.8 d17, d16, #7 # CHECK-NEXT: 1 4 1.00 vsli.16 d17, d16, #15 # CHECK-NEXT: 1 4 1.00 vsli.32 d17, d16, #31 # CHECK-NEXT: 1 4 1.00 vsli.64 d17, d16, #63 # CHECK-NEXT: 1 5 1.00 vsli.8 q9, q8, #7 # CHECK-NEXT: 1 5 1.00 vsli.16 q9, q8, #15 # CHECK-NEXT: 1 5 1.00 vsli.32 q9, q8, #31 # CHECK-NEXT: 1 5 1.00 vsli.64 q9, q8, #63 # CHECK-NEXT: 1 4 1.00 vsri.8 d17, d16, #8 # CHECK-NEXT: 1 4 1.00 vsri.16 d17, d16, #16 # CHECK-NEXT: 1 4 1.00 vsri.32 d17, d16, #32 # CHECK-NEXT: 1 4 1.00 vsri.64 d17, d16, #64 # CHECK-NEXT: 1 5 1.00 vsri.8 q9, q8, #8 # CHECK-NEXT: 1 5 1.00 vsri.16 q9, q8, #16 # CHECK-NEXT: 1 5 1.00 vsri.32 q9, q8, #32 # CHECK-NEXT: 1 5 1.00 vsri.64 q9, q8, #64 # CHECK-NEXT: 1 3 0.50 vext.8 d16, d17, d16, #3 # CHECK-NEXT: 1 3 0.50 vext.8 d16, d17, d16, #5 # CHECK-NEXT: 1 3 0.50 vext.8 q8, q9, q8, #3 # CHECK-NEXT: 1 3 0.50 vext.8 q8, q9, q8, #7 # CHECK-NEXT: 1 3 0.50 vext.16 d16, d17, d16, #3 # CHECK-NEXT: 1 3 0.50 vext.32 q8, q9, q8, #3 # CHECK-NEXT: 2 3 1.00 U vtrn.8 d17, d16 # CHECK-NEXT: 2 3 1.00 U vtrn.16 d17, d16 # CHECK-NEXT: 2 3 1.00 U vtrn.32 d17, d16 # CHECK-NEXT: 2 3 1.00 U vtrn.8 q9, q8 # CHECK-NEXT: 2 3 1.00 U vtrn.16 q9, q8 # CHECK-NEXT: 2 3 1.00 U vtrn.32 q9, q8 # CHECK-NEXT: 2 3 1.00 U vuzp.8 d17, d16 # CHECK-NEXT: 2 3 1.00 U vuzp.16 d17, d16 # CHECK-NEXT: 2 6 1.00 U vuzp.8 q9, q8 # CHECK-NEXT: 2 6 1.00 U vuzp.16 q9, q8 # CHECK-NEXT: 2 6 1.00 U vuzp.32 q9, q8 # CHECK-NEXT: 2 3 1.00 U vzip.8 d17, d16 # CHECK-NEXT: 2 3 1.00 U vzip.16 d17, d16 # CHECK-NEXT: 2 6 1.00 U vzip.8 q9, q8 # CHECK-NEXT: 2 6 1.00 U vzip.16 q9, q8 # CHECK-NEXT: 2 6 1.00 U vzip.32 q9, q8 # CHECK-NEXT: 1 3 0.50 vsub.i8 d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vsub.i16 d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vsub.i32 d16, d17, d16 # CHECK-NEXT: 1 3 0.50 vsub.i64 d16, d17, d16 # CHECK-NEXT: 1 5 0.50 vsub.f32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vsub.i8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vsub.i16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vsub.i32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vsub.i64 q8, q8, q9 # CHECK-NEXT: 1 5 0.50 vsub.f32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vsubl.s8 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vsubl.s16 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vsubl.s32 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vsubl.u8 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vsubl.u16 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vsubl.u32 q8, d17, d16 # CHECK-NEXT: 1 3 0.50 vsubw.s8 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vsubw.s16 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vsubw.s32 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vsubw.u8 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vsubw.u16 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vsubw.u32 q8, q8, d18 # CHECK-NEXT: 1 3 0.50 vhsub.s8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhsub.s16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhsub.s32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhsub.u8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhsub.u16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhsub.u32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vhsub.s8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vhsub.s16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vhsub.s32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqsub.s8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqsub.s16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqsub.s32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqsub.s64 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqsub.u8 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqsub.u16 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqsub.u32 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqsub.u64 d16, d16, d17 # CHECK-NEXT: 1 3 0.50 vqsub.s8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqsub.s16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqsub.s32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqsub.s64 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqsub.u8 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqsub.u16 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqsub.u32 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vqsub.u64 q8, q8, q9 # CHECK-NEXT: 1 3 0.50 vsubhn.i16 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vsubhn.i32 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vsubhn.i64 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vrsubhn.i16 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vrsubhn.i32 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vrsubhn.i64 d16, q8, q9 # CHECK-NEXT: 1 3 0.50 vtbl.8 d16, {d17}, d16 # CHECK-NEXT: 1 3 0.50 U vtbl.8 d16, {d16, d17}, d18 # CHECK-NEXT: 1 6 0.50 U vtbl.8 d16, {d16, d17, d18}, d20 # CHECK-NEXT: 1 6 0.50 U vtbl.8 d16, {d16, d17, d18, d19}, d20 # CHECK-NEXT: 1 3 0.50 vtbx.8 d18, {d16}, d17 # CHECK-NEXT: 1 3 0.50 U vtbx.8 d19, {d16, d17}, d18 # CHECK-NEXT: 1 6 0.50 U vtbx.8 d20, {d16, d17, d18}, d21 # CHECK-NEXT: 1 6 0.50 U vtbx.8 d20, {d16, d17, d18, d19}, d21 # CHECK-NEXT: 1 5 1.00 * vld1.8 {d16}, [r0:64] # CHECK-NEXT: 1 5 1.00 * vld1.16 {d16}, [r0] # CHECK-NEXT: 1 5 1.00 * vld1.32 {d16}, [r0] # CHECK-NEXT: 1 5 1.00 * vld1.64 {d16}, [r0] # CHECK-NEXT: 1 5 1.00 * vld1.8 {d16, d17}, [r0:64] # CHECK-NEXT: 1 5 1.00 * vld1.16 {d16, d17}, [r0:128] # CHECK-NEXT: 1 5 1.00 * vld1.32 {d16, d17}, [r0] # CHECK-NEXT: 1 5 1.00 * vld1.64 {d16, d17}, [r0] # CHECK-NEXT: 2 8 1.00 * vld2.8 {d16, d17}, [r0:64] # CHECK-NEXT: 2 8 1.00 * vld2.16 {d16, d17}, [r0:128] # CHECK-NEXT: 2 8 1.00 * vld2.32 {d16, d17}, [r0] # CHECK-NEXT: 2 8 1.00 * vld2.8 {d16, d17, d18, d19}, [r0:64] # CHECK-NEXT: 2 8 1.00 * vld2.16 {d16, d17, d18, d19}, [r0:128] # CHECK-NEXT: 2 8 1.00 * vld2.32 {d16, d17, d18, d19}, [r0:256] # CHECK-NEXT: 6 9 3.00 * vld3.8 {d16, d17, d18}, [r0:64] # CHECK-NEXT: 6 9 3.00 * vld3.16 {d16, d17, d18}, [r0] # CHECK-NEXT: 6 9 3.00 * vld3.32 {d16, d17, d18}, [r0] # CHECK-NEXT: 9 9 3.00 * vld3.8 {d16, d18, d20}, [r0:64]! # CHECK-NEXT: 9 9 3.00 * vld3.8 {d17, d19, d21}, [r0:64]! # CHECK-NEXT: 9 9 3.00 * vld3.16 {d16, d18, d20}, [r0]! # CHECK-NEXT: 9 9 3.00 * vld3.16 {d17, d19, d21}, [r0]! # CHECK-NEXT: 9 9 3.00 * vld3.32 {d16, d18, d20}, [r0]! # CHECK-NEXT: 9 9 3.00 * vld3.32 {d17, d19, d21}, [r0]! # CHECK-NEXT: 8 9 4.00 * vld4.8 {d16, d17, d18, d19}, [r0:64] # CHECK-NEXT: 8 9 4.00 * vld4.16 {d16, d17, d18, d19}, [r0:128] # CHECK-NEXT: 8 9 4.00 * vld4.32 {d16, d17, d18, d19}, [r0:256] # CHECK-NEXT: 12 9 4.00 * vld4.8 {d16, d18, d20, d22}, [r0:256]! # CHECK-NEXT: 12 9 4.00 * vld4.8 {d17, d19, d21, d23}, [r0:256]! # CHECK-NEXT: 12 9 4.00 * vld4.16 {d16, d18, d20, d22}, [r0]! # CHECK-NEXT: 12 9 4.00 * vld4.16 {d17, d19, d21, d23}, [r0]! # CHECK-NEXT: 12 9 4.00 * vld4.32 {d16, d18, d20, d22}, [r0]! # CHECK-NEXT: 12 9 4.00 * vld4.32 {d17, d19, d21, d23}, [r0]! # CHECK-NEXT: 2 8 1.00 * vld1.8 {d16[3]}, [r0] # CHECK-NEXT: 2 8 1.00 * vld1.16 {d16[2]}, [r0:16] # CHECK-NEXT: 2 8 1.00 * vld1.32 {d16[1]}, [r0:32] # CHECK-NEXT: 4 8 2.00 * vld2.8 {d16[1], d17[1]}, [r0:16] # CHECK-NEXT: 4 8 2.00 * vld2.16 {d16[1], d17[1]}, [r0:32] # CHECK-NEXT: 4 8 2.00 * vld2.32 {d16[1], d17[1]}, [r0] # CHECK-NEXT: 4 8 2.00 * vld2.16 {d17[1], d19[1]}, [r0] # CHECK-NEXT: 4 8 2.00 * vld2.32 {d17[0], d19[0]}, [r0:64] # CHECK-NEXT: 6 9 3.00 * vld3.8 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: 6 9 3.00 * vld3.16 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: 6 8 3.00 * vld3.32 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: 6 9 3.00 * vld3.16 {d16[1], d18[1], d20[1]}, [r0] # CHECK-NEXT: 6 8 3.00 * vld3.32 {d17[1], d19[1], d21[1]}, [r0] # CHECK-NEXT: 6 8 3.00 * vld3.8 {d0[], d1[], d2[]}, [r4] # CHECK-NEXT: 9 8 3.00 * vld3.8 {d0[], d1[], d2[]}, [r4]! # CHECK-NEXT: 9 8 3.00 * vld3.8 {d0[], d2[], d4[]}, [r4], r5 # CHECK-NEXT: 6 8 3.00 * vld3.16 {d0[], d2[], d4[]}, [r4] # CHECK-NEXT: 9 8 3.00 * vld3.16 {d0[], d1[], d2[]}, [r4]! # CHECK-NEXT: 9 8 3.00 * vld3.16 {d0[], d2[], d4[]}, [r4], r5 # CHECK-NEXT: 6 8 3.00 * vld3.32 {d0[], d1[], d2[]}, [r4] # CHECK-NEXT: 9 8 3.00 * vld3.32 {d0[], d1[], d2[]}, [r4]! # CHECK-NEXT: 9 8 3.00 * vld3.32 {d0[], d2[], d4[]}, [r4], r5 # CHECK-NEXT: 8 9 4.00 * vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] # CHECK-NEXT: 8 9 4.00 * vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] # CHECK-NEXT: 8 8 4.00 * vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] # CHECK-NEXT: 8 9 4.00 * vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] # CHECK-NEXT: 8 8 4.00 * vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] # CHECK-NEXT: 8 8 4.00 * vld4.8 {d0[], d1[], d2[], d3[]}, [r4] # CHECK-NEXT: 8 8 4.00 * vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] # CHECK-NEXT: 12 8 4.00 * vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! # CHECK-NEXT: 12 8 4.00 * vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r5 # CHECK-NEXT: 8 8 4.00 * vld4.16 {d0[], d1[], d2[], d3[]}, [r4] # CHECK-NEXT: 8 8 4.00 * vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] # CHECK-NEXT: 12 8 4.00 * vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! # CHECK-NEXT: 12 8 4.00 * vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r5 # CHECK-NEXT: 8 8 4.00 * vld4.32 {d0[], d1[], d2[], d3[]}, [r4] # CHECK-NEXT: 8 8 4.00 * vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] # CHECK-NEXT: 12 8 4.00 * vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! # CHECK-NEXT: 12 8 4.00 * vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r5 # CHECK-NEXT: 1 1 1.00 * vst1.8 {d16}, [r0:64] # CHECK-NEXT: 1 1 1.00 * vst1.16 {d16}, [r0] # CHECK-NEXT: 1 1 1.00 * vst1.32 {d16}, [r0] # CHECK-NEXT: 1 1 1.00 * vst1.64 {d16}, [r0] # CHECK-NEXT: 1 2 1.00 * vst1.8 {d16, d17}, [r0:64] # CHECK-NEXT: 1 2 1.00 * vst1.16 {d16, d17}, [r0:128] # CHECK-NEXT: 1 2 1.00 * vst1.32 {d16, d17}, [r0] # CHECK-NEXT: 1 2 1.00 * vst1.64 {d16, d17}, [r0] # CHECK-NEXT: 2 3 1.00 * vst2.8 {d16, d17}, [r0:64] # CHECK-NEXT: 2 3 1.00 * vst2.16 {d16, d17}, [r0:128] # CHECK-NEXT: 2 3 1.00 * vst2.32 {d16, d17}, [r0] # CHECK-NEXT: 2 4 1.00 * vst2.8 {d16, d17, d18, d19}, [r0:64] # CHECK-NEXT: 2 4 1.00 * vst2.16 {d16, d17, d18, d19}, [r0:128] # CHECK-NEXT: 2 4 1.00 * vst2.32 {d16, d17, d18, d19}, [r0:256] # CHECK-NEXT: 2 3 1.00 * vst3.8 {d16, d17, d18}, [r0:64] # CHECK-NEXT: 2 3 1.00 * vst3.16 {d16, d17, d18}, [r0] # CHECK-NEXT: 2 3 1.00 * vst3.32 {d16, d17, d18}, [r0] # CHECK-NEXT: 3 3 1.00 * vst3.8 {d16, d18, d20}, [r0:64]! # CHECK-NEXT: 3 3 1.00 * vst3.8 {d17, d19, d21}, [r0:64]! # CHECK-NEXT: 3 3 1.00 * vst3.16 {d16, d18, d20}, [r0]! # CHECK-NEXT: 3 3 1.00 * vst3.16 {d17, d19, d21}, [r0]! # CHECK-NEXT: 3 3 1.00 * vst3.32 {d16, d18, d20}, [r0]! # CHECK-NEXT: 3 3 1.00 * vst3.32 {d17, d19, d21}, [r0]! # CHECK-NEXT: 2 4 1.00 * vst4.8 {d16, d17, d18, d19}, [r0:64] # CHECK-NEXT: 2 4 1.00 * vst4.16 {d16, d17, d18, d19}, [r0:128] # CHECK-NEXT: 3 4 1.00 * vst4.8 {d16, d18, d20, d22}, [r0:256]! # CHECK-NEXT: 3 4 1.00 * vst4.8 {d17, d19, d21, d23}, [r0:256]! # CHECK-NEXT: 3 4 1.00 * vst4.16 {d16, d18, d20, d22}, [r0]! # CHECK-NEXT: 3 4 1.00 * vst4.16 {d17, d19, d21, d23}, [r0]! # CHECK-NEXT: 3 4 1.00 * vst4.32 {d16, d18, d20, d22}, [r0]! # CHECK-NEXT: 3 4 1.00 * vst4.32 {d17, d19, d21, d23}, [r0]! # CHECK-NEXT: 2 3 1.00 * vst2.8 {d16[1], d17[1]}, [r0:16] # CHECK-NEXT: 2 3 1.00 * vst2.16 {d16[1], d17[1]}, [r0:32] # CHECK-NEXT: 2 3 1.00 * vst2.32 {d16[1], d17[1]}, [r0] # CHECK-NEXT: 2 3 1.00 * vst2.16 {d17[1], d19[1]}, [r0] # CHECK-NEXT: 2 3 1.00 * vst2.32 {d17[0], d19[0]}, [r0:64] # CHECK-NEXT: 2 3 1.00 * vst3.8 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: 2 3 1.00 * vst3.16 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: 2 3 1.00 * vst3.32 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: 2 3 1.00 * vst3.16 {d17[2], d19[2], d21[2]}, [r0] # CHECK-NEXT: 2 3 1.00 * vst3.32 {d16[0], d18[0], d20[0]}, [r0] # CHECK-NEXT: 2 3 1.00 * vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] # CHECK-NEXT: 2 3 1.00 * vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] # CHECK-NEXT: 2 3 1.00 * vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] # CHECK-NEXT: 2 3 1.00 * vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] # CHECK-NEXT: 2 3 1.00 * vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] # CHECK-NEXT: 3 8 1.00 * vld1.8 {d0[]}, [r0], r0 # CHECK-NEXT: 3 3 1.00 * vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! # CHECK-NEXT: 2 5 2.00 vmovvs r2, lr, s27, s28 # CHECK-NEXT: 1 5 1.00 vmov s3, s4, r1, r2 # CHECK-NEXT: 1 5 1.00 vmov s2, s3, r1, r2 # CHECK-NEXT: 2 5 2.00 vmov r1, r2, s3, s4 # CHECK-NEXT: 2 5 2.00 vmov r1, r2, s2, s3 # CHECK-NEXT: 2 8 1.00 vmov d15, r1, r2 # CHECK-NEXT: 2 8 1.00 vmov d16, r1, r2 # CHECK-NEXT: 2 5 2.00 vmov r1, r2, d15 # CHECK-NEXT: 2 5 2.00 vmov r1, r2, d16 # CHECK-NEXT: 1 5 0.50 vcvttmi.f32.f16 s2, s19 # CHECK-NEXT: 2 6 1.00 * vld1.8 {d23, d24, d25}, [r6:64]! # CHECK-NEXT: 2 6 1.00 * vld1.32 {d22, d23, d24, d25}, [pc:64]! # CHECK-NEXT: 2 2 1.00 * vst1.32 {d26, d27}, [r1:64]! # CHECK-NEXT: 1 3 0.50 vmov.f32 d0, #1.600000e+01 # CHECK-NEXT: 1 3 0.50 vmov.f32 q0, #1.600000e+01 # CHECK-NEXT: 2 1 1.00 * vst1.8 {d8}, [r4]! # CHECK-NEXT: 2 1 1.00 * vst1.16 {d8}, [r4]! # CHECK-NEXT: 2 1 1.00 * vst1.32 {d8}, [r4]! # CHECK-NEXT: 2 1 1.00 * vst1.64 {d8}, [r4]! # CHECK-NEXT: 2 1 1.00 * vst1.8 {d8}, [r4], r6 # CHECK-NEXT: 2 1 1.00 * vst1.16 {d8}, [r4], r6 # CHECK-NEXT: 2 1 1.00 * vst1.32 {d8}, [r4], r6 # CHECK-NEXT: 2 1 1.00 * vst1.64 {d8}, [r4], r6 # CHECK-NEXT: 2 2 1.00 * vst1.8 {d8, d9}, [r4]! # CHECK-NEXT: 2 2 1.00 * vst1.16 {d8, d9}, [r4]! # CHECK-NEXT: 2 2 1.00 * vst1.32 {d8, d9}, [r4]! # CHECK-NEXT: 2 2 1.00 * vst1.64 {d8, d9}, [r4]! # CHECK-NEXT: 2 2 1.00 * vst1.8 {d8, d9}, [r4], r6 # CHECK-NEXT: 2 2 1.00 * vst1.16 {d8, d9}, [r4], r6 # CHECK-NEXT: 2 2 1.00 * vst1.32 {d8, d9}, [r4], r6 # CHECK-NEXT: 2 2 1.00 * vst1.64 {d8, d9}, [r4], r6 # CHECK-NEXT: 2 3 1.00 * vst1.8 {d8, d9, d10}, [r4]! # CHECK-NEXT: 2 3 1.00 * vst1.16 {d8, d9, d10}, [r4]! # CHECK-NEXT: 2 3 1.00 * vst1.32 {d8, d9, d10}, [r4]! # CHECK-NEXT: 2 3 1.00 * vst1.64 {d8, d9, d10}, [r4]! # CHECK-NEXT: 2 3 1.00 * vst1.8 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: 2 3 1.00 * vst1.16 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: 2 3 1.00 * vst1.32 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: 2 3 1.00 * vst1.64 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: 2 4 1.00 * vst1.8 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 2 4 1.00 * vst1.16 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 2 4 1.00 * vst1.32 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 2 4 1.00 * vst1.64 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 2 4 1.00 * vst1.8 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: 2 4 1.00 * vst1.16 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: 2 4 1.00 * vst1.32 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: 2 4 1.00 * vst1.64 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: 3 3 1.00 * vst2.8 {d8, d9}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst2.16 {d8, d9}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst2.32 {d8, d9}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst2.8 {d8, d9}, [r4], r6 # CHECK-NEXT: 3 3 1.00 * vst2.16 {d8, d9}, [r4], r6 # CHECK-NEXT: 3 3 1.00 * vst2.32 {d8, d9}, [r4], r6 # CHECK-NEXT: 3 3 1.00 * vst2.8 {d8, d10}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst2.16 {d8, d10}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst2.32 {d8, d10}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst2.8 {d8, d10}, [r4], r6 # CHECK-NEXT: 3 3 1.00 * vst2.16 {d8, d10}, [r4], r6 # CHECK-NEXT: 3 3 1.00 * vst2.32 {d8, d10}, [r4], r6 # CHECK-NEXT: 3 3 1.00 * vst3.8 {d8, d9, d10}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst3.16 {d8, d9, d10}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst3.32 {d8, d9, d10}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst3.8 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: 3 3 1.00 * vst3.16 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: 3 3 1.00 * vst3.32 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: 3 4 1.00 * vst4.8 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 3 4 1.00 * vst4.16 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 3 4 1.00 * vst4.32 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 3 4 1.00 * vst4.8 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: 3 4 1.00 * vst4.16 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: 3 4 1.00 * vst4.32 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: 1 2 1.00 * vst1.16 {d8, d9}, [r4] # CHECK-NEXT: 1 2 1.00 * vst1.32 {d8, d9}, [r4] # CHECK-NEXT: 1 2 1.00 * vst1.64 {d8, d9}, [r4] # CHECK-NEXT: 1 2 1.00 * vst1.8 {d8, d9}, [r4] # CHECK-NEXT: 2 3 1.00 * vst2.16 {d8, d9}, [r4] # CHECK-NEXT: 2 3 1.00 * vst2.32 {d8, d9}, [r4] # CHECK-NEXT: 2 3 1.00 * vst2.8 {d8, d9}, [r4] # CHECK-NEXT: 3 3 1.00 * vst2.16 {d8, d9}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst2.16 {d8, d9}, [r4], r6 # CHECK-NEXT: 3 3 1.00 * vst2.32 {d8, d9}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst2.32 {d8, d9}, [r4], r6 # CHECK-NEXT: 3 3 1.00 * vst2.8 {d8, d9}, [r4]! # CHECK-NEXT: 3 3 1.00 * vst2.8 {d8, d9}, [r4], r6 # CHECK-NEXT: 2 3 1.00 * vst2.16 {d8, d10}, [r4] # CHECK-NEXT: 2 3 1.00 * vst2.32 {d8, d10}, [r4] # CHECK-NEXT: 2 3 1.00 * vst2.8 {d8, d10}, [r4] # CHECK-NEXT: 2 3 1.00 * vst3.8 {d8, d9, d10}, [r4] # CHECK-NEXT: 2 3 1.00 * vst3.16 {d8, d9, d10}, [r4] # CHECK-NEXT: 2 3 1.00 * vst3.32 {d8, d9, d10}, [r4] # CHECK-NEXT: 2 4 1.00 * vst4.8 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: 2 4 1.00 * vst4.16 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: 2 4 1.00 * vst4.32 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: 2 3 1.00 * vst3.8 {d8, d10, d12}, [r4] # CHECK-NEXT: 2 3 1.00 * vst3.16 {d8, d10, d12}, [r4] # CHECK-NEXT: 2 3 1.00 * vst3.32 {d8, d10, d12}, [r4] # CHECK-NEXT: 2 4 1.00 * vst4.8 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: 2 4 1.00 * vst4.16 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: 2 4 1.00 * vst4.32 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: 2 5 1.00 * vld1.8 {d8}, [r4]! # CHECK-NEXT: 2 5 1.00 * vld1.16 {d8}, [r4]! # CHECK-NEXT: 2 5 1.00 * vld1.32 {d8}, [r4]! # CHECK-NEXT: 2 5 1.00 * vld1.64 {d8}, [r4]! # CHECK-NEXT: 2 5 1.00 * vld1.8 {d8}, [r4], r6 # CHECK-NEXT: 2 5 1.00 * vld1.16 {d8}, [r4], r6 # CHECK-NEXT: 2 5 1.00 * vld1.32 {d8}, [r4], r6 # CHECK-NEXT: 2 5 1.00 * vld1.64 {d8}, [r4], r6 # CHECK-NEXT: 2 5 1.00 * vld1.8 {d8, d9}, [r4]! # CHECK-NEXT: 2 5 1.00 * vld1.16 {d8, d9}, [r4]! # CHECK-NEXT: 2 5 1.00 * vld1.32 {d8, d9}, [r4]! # CHECK-NEXT: 2 5 1.00 * vld1.64 {d8, d9}, [r4]! # CHECK-NEXT: 2 5 1.00 * vld1.8 {d8, d9}, [r4], r6 # CHECK-NEXT: 2 5 1.00 * vld1.16 {d8, d9}, [r4], r6 # CHECK-NEXT: 2 5 1.00 * vld1.32 {d8, d9}, [r4], r6 # CHECK-NEXT: 2 5 1.00 * vld1.64 {d8, d9}, [r4], r6 # CHECK-NEXT: 2 6 1.00 * vld1.8 {d8, d9, d10}, [r4]! # CHECK-NEXT: 2 6 1.00 * vld1.16 {d8, d9, d10}, [r4]! # CHECK-NEXT: 2 6 1.00 * vld1.32 {d8, d9, d10}, [r4]! # CHECK-NEXT: 2 6 1.00 * vld1.64 {d8, d9, d10}, [r4]! # CHECK-NEXT: 2 6 1.00 * vld1.8 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: 2 6 1.00 * vld1.16 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: 2 6 1.00 * vld1.32 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: 2 6 1.00 * vld1.64 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: 2 6 1.00 * vld1.8 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 2 6 1.00 * vld1.16 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 2 6 1.00 * vld1.32 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 2 6 1.00 * vld1.64 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 2 6 1.00 * vld1.8 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: 2 6 1.00 * vld1.16 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: 2 6 1.00 * vld1.32 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: 2 6 1.00 * vld1.64 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: 3 8 1.00 * vld2.8 {d8, d9}, [r4]! # CHECK-NEXT: 3 8 1.00 * vld2.16 {d8, d9}, [r4]! # CHECK-NEXT: 3 8 1.00 * vld2.32 {d8, d9}, [r4]! # CHECK-NEXT: 3 8 1.00 * vld2.8 {d8, d9}, [r4], r6 # CHECK-NEXT: 3 8 1.00 * vld2.16 {d8, d9}, [r4], r6 # CHECK-NEXT: 3 8 1.00 * vld2.32 {d8, d9}, [r4], r6 # CHECK-NEXT: 3 9 1.00 * vld2.8 {d8, d10}, [r4]! # CHECK-NEXT: 3 9 1.00 * vld2.16 {d8, d10}, [r4]! # CHECK-NEXT: 3 9 1.00 * vld2.32 {d8, d10}, [r4]! # CHECK-NEXT: 3 9 1.00 * vld2.8 {d8, d10}, [r4], r6 # CHECK-NEXT: 3 9 1.00 * vld2.16 {d8, d10}, [r4], r6 # CHECK-NEXT: 3 9 1.00 * vld2.32 {d8, d10}, [r4], r6 # CHECK-NEXT: 9 9 3.00 * vld3.8 {d8, d9, d10}, [r4]! # CHECK-NEXT: 9 9 3.00 * vld3.16 {d8, d9, d10}, [r4]! # CHECK-NEXT: 9 9 3.00 * vld3.32 {d8, d9, d10}, [r4]! # CHECK-NEXT: 9 9 3.00 * vld3.8 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: 9 9 3.00 * vld3.16 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: 9 9 3.00 * vld3.32 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: 12 9 4.00 * vld4.8 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 12 9 4.00 * vld4.16 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 12 9 4.00 * vld4.32 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 12 9 4.00 * vld4.8 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: 12 9 4.00 * vld4.16 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: 12 9 4.00 * vld4.32 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: 1 5 1.00 * vld1.16 {d8, d9}, [r4] # CHECK-NEXT: 1 5 1.00 * vld1.32 {d8, d9}, [r4] # CHECK-NEXT: 1 5 1.00 * vld1.64 {d8, d9}, [r4] # CHECK-NEXT: 1 5 1.00 * vld1.8 {d8, d9}, [r4] # CHECK-NEXT: 2 8 1.00 * vld2.16 {d8, d9}, [r4] # CHECK-NEXT: 2 8 1.00 * vld2.32 {d8, d9}, [r4] # CHECK-NEXT: 2 8 1.00 * vld2.8 {d8, d9}, [r4] # CHECK-NEXT: 3 8 1.00 * vld2.16 {d8, d9}, [r4]! # CHECK-NEXT: 3 8 1.00 * vld2.16 {d8, d9}, [r4], r6 # CHECK-NEXT: 3 8 1.00 * vld2.32 {d8, d9}, [r4]! # CHECK-NEXT: 3 8 1.00 * vld2.32 {d8, d9}, [r4], r6 # CHECK-NEXT: 3 8 1.00 * vld2.8 {d8, d9}, [r4]! # CHECK-NEXT: 3 8 1.00 * vld2.8 {d8, d9}, [r4], r6 # CHECK-NEXT: 2 9 1.00 * vld2.16 {d8, d10}, [r4] # CHECK-NEXT: 2 9 1.00 * vld2.32 {d8, d10}, [r4] # CHECK-NEXT: 2 9 1.00 * vld2.8 {d8, d10}, [r4] # CHECK-NEXT: 3 8 1.00 * vld2.16 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 3 8 1.00 * vld2.16 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: 3 8 1.00 * vld2.32 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 3 8 1.00 * vld2.32 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: 3 8 1.00 * vld2.8 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: 3 8 1.00 * vld2.8 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: 6 9 3.00 * vld3.8 {d8, d9, d10}, [r4] # CHECK-NEXT: 6 9 3.00 * vld3.16 {d8, d9, d10}, [r4] # CHECK-NEXT: 6 9 3.00 * vld3.32 {d8, d9, d10}, [r4] # CHECK-NEXT: 8 9 4.00 * vld4.8 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: 8 9 4.00 * vld4.16 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: 8 9 4.00 * vld4.32 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: 6 9 3.00 * vld3.8 {d8, d10, d12}, [r4] # CHECK-NEXT: 6 9 3.00 * vld3.16 {d8, d10, d12}, [r4] # CHECK-NEXT: 6 9 3.00 * vld3.32 {d8, d10, d12}, [r4] # CHECK-NEXT: 8 9 4.00 * vld4.8 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: 8 9 4.00 * vld4.16 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: 8 9 4.00 * vld4.32 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: 4 8 2.00 * vld2.8 {d0[], d1[]}, [r2] # CHECK-NEXT: 4 8 2.00 * vld2.16 {d0[], d1[]}, [r2] # CHECK-NEXT: 4 8 2.00 * vld2.32 {d0[], d1[]}, [r2] # CHECK-NEXT: 3 8 1.00 * vld2.8 {d0[], d1[]}, [r2]! # CHECK-NEXT: 3 8 1.00 * vld2.16 {d0[], d1[]}, [r2]! # CHECK-NEXT: 3 8 1.00 * vld2.32 {d0[], d1[]}, [r2]! # CHECK-NEXT: 3 8 1.00 * vld2.8 {d0[], d1[]}, [r2], r3 # CHECK-NEXT: 3 8 1.00 * vld2.16 {d0[], d1[]}, [r2], r3 # CHECK-NEXT: 3 8 1.00 * vld2.32 {d0[], d1[]}, [r2], r3 # CHECK-NEXT: 4 8 2.00 * vld2.8 {d0[], d2[]}, [r3] # CHECK-NEXT: 4 8 2.00 * vld2.16 {d0[], d2[]}, [r3] # CHECK-NEXT: 4 8 2.00 * vld2.32 {d0[], d2[]}, [r3] # CHECK-NEXT: 3 8 1.00 * vld2.8 {d0[], d2[]}, [r3]! # CHECK-NEXT: 3 8 1.00 * vld2.16 {d0[], d2[]}, [r3]! # CHECK-NEXT: 3 8 1.00 * vld2.32 {d0[], d2[]}, [r3]! # CHECK-NEXT: 3 8 1.00 * vld2.8 {d0[], d2[]}, [r3], r4 # CHECK-NEXT: 3 8 1.00 * vld2.16 {d0[], d2[]}, [r3], r4 # CHECK-NEXT: 3 8 1.00 * vld2.32 {d0[], d2[]}, [r3], r4 # CHECK: Resources: # CHECK-NEXT: [0] - A57UnitB # CHECK-NEXT: [1.0] - A57UnitI # CHECK-NEXT: [1.1] - A57UnitI # CHECK-NEXT: [2] - A57UnitL # CHECK-NEXT: [3] - A57UnitM # CHECK-NEXT: [4] - A57UnitS # CHECK-NEXT: [5] - A57UnitW # CHECK-NEXT: [6] - A57UnitX # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] # CHECK-NEXT: - 140.00 140.00 408.00 - 132.00 490.50 721.50 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: - - - - - - 0.50 0.50 vabs.s8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vabs.s16 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vabs.s32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vabs.f32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vabs.s8 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vabs.s16 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vabs.s32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vabs.f32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vqabs.s8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vqabs.s16 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vqabs.s32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vqabs.s8 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vqabs.s16 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vqabs.s32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.u8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.u16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.u32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vabd.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vabdl.s8 q8, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabdl.s16 q8, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabdl.s32 q8, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabdl.u8 q8, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabdl.u16 q8, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vabdl.u32 q8, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vaba.s8 d16, d18, d17 # CHECK-NEXT: - - - - - - - 1.00 vaba.s16 d16, d18, d17 # CHECK-NEXT: - - - - - - - 1.00 vaba.s32 d16, d18, d17 # CHECK-NEXT: - - - - - - - 1.00 vaba.u8 d16, d18, d17 # CHECK-NEXT: - - - - - - - 1.00 vaba.u16 d16, d18, d17 # CHECK-NEXT: - - - - - - - 1.00 vaba.u32 d16, d18, d17 # CHECK-NEXT: - - - - - - - 1.00 vaba.s8 q9, q8, q10 # CHECK-NEXT: - - - - - - - 1.00 vaba.s16 q9, q8, q10 # CHECK-NEXT: - - - - - - - 1.00 vaba.s32 q9, q8, q10 # CHECK-NEXT: - - - - - - - 1.00 vaba.u8 q9, q8, q10 # CHECK-NEXT: - - - - - - - 1.00 vaba.u16 q9, q8, q10 # CHECK-NEXT: - - - - - - - 1.00 vaba.u32 q9, q8, q10 # CHECK-NEXT: - - - - - - - 1.00 vabal.s8 q8, d19, d18 # CHECK-NEXT: - - - - - - - 1.00 vabal.s16 q8, d19, d18 # CHECK-NEXT: - - - - - - - 1.00 vabal.s32 q8, d19, d18 # CHECK-NEXT: - - - - - - - 1.00 vabal.u8 q8, d19, d18 # CHECK-NEXT: - - - - - - - 1.00 vabal.u16 q8, d19, d18 # CHECK-NEXT: - - - - - - - 1.00 vabal.u32 q8, d19, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vadd.i8 d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vadd.i16 d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vadd.i64 d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vadd.i32 d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vadd.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vadd.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddl.s8 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddl.s16 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddl.s32 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddl.u8 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddl.u16 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddl.u32 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddw.s8 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddw.s16 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddw.s32 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddw.u8 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddw.u16 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddw.u32 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.u8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.u16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vhadd.u32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.u8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.u16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vrhadd.u32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.s64 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.u64 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.s64 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.u8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.u16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.u32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqadd.u64 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddhn.i16 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddhn.i32 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vaddhn.i64 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vraddhn.i16 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vraddhn.i32 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vraddhn.i64 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcnt.8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vcnt.8 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vclz.i8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vclz.i16 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vclz.i32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vclz.i8 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vclz.i16 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vclz.i32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vcls.s8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vcls.s16 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vcls.s32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vcls.s8 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vcls.s16 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vcls.s32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vand d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vand q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 veor d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 veor q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vorr d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vorr q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vorr.i32 d16, #0x1000000 # CHECK-NEXT: - - - - - - 0.50 0.50 vorr.i32 q8, #0x1000000 # CHECK-NEXT: - - - - - - 0.50 0.50 vorr.i32 q8, #0x0 # CHECK-NEXT: - - - - - - 0.50 0.50 vbic d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vbic q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vbic.i32 d16, #0xff000000 # CHECK-NEXT: - - - - - - 0.50 0.50 vbic.i32 q8, #0xff000000 # CHECK-NEXT: - - - - - - 0.50 0.50 vorn d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vorn q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmvn d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vmvn q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vbsl d18, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vbsl q8, q10, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vbit d18, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vbit q8, q10, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vbif d18, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vbif q8, q10, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vceq.i8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vceq.i16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vceq.i32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vceq.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vceq.i8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vceq.i16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vceq.i32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vceq.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.u8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.u16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.u32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vacge.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vacge.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.u8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.u16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.u32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vacgt.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vacgt.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vtst.8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vtst.16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vtst.32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vtst.8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vtst.16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vtst.32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vceq.i8 d16, d16, #0 # CHECK-NEXT: - - - - - - 0.50 0.50 vcge.s8 d16, d16, #0 # CHECK-NEXT: - - - - - - 0.50 0.50 vcle.s8 d16, d16, #0 # CHECK-NEXT: - - - - - - 0.50 0.50 vcgt.s8 d16, d16, #0 # CHECK-NEXT: - - - - - - 0.50 0.50 vclt.s8 d16, d16, #0 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.s32.f32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.u32.f32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.f32.s32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.f32.u32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.s32.f32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.u32.f32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.f32.s32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.f32.u32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.s32.f32 d16, d16, #1 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.u32.f32 d16, d16, #1 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.f32.s32 d16, d16, #1 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.f32.u32 d16, d16, #1 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.s32.f32 q8, q8, #1 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.u32.f32 q8, q8, #1 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.f32.s32 q8, q8, #1 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.f32.u32 q8, q8, #1 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.f32.f16 q8, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvt.f16.f32 d16, q8 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vdup.8 d16, r0 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vdup.16 d16, r0 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vdup.32 d16, r0 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vdup.8 q8, r0 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vdup.16 q8, r0 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vdup.32 q8, r0 # CHECK-NEXT: - - - - - - 0.50 0.50 vdup.8 d16, d16[1] # CHECK-NEXT: - - - - - - 0.50 0.50 vdup.16 d16, d16[1] # CHECK-NEXT: - - - - - - 0.50 0.50 vdup.32 d16, d16[1] # CHECK-NEXT: - - - - - - 0.50 0.50 vdup.8 q8, d16[1] # CHECK-NEXT: - - - - - - 0.50 0.50 vdup.16 q8, d16[1] # CHECK-NEXT: - - - - - - 0.50 0.50 vdup.32 q8, d16[1] # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.u8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.u16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.u32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmin.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.u8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.u16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.u32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmax.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i8 d16, #0x8 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i16 d16, #0x10 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i16 d16, #0x1000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 d16, #0x20 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 d16, #0x2000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 d16, #0x200000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 d16, #0x20000000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 d16, #0x20ff # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 d16, #0x20ffff # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i64 d16, #0xff0000ff0000ffff # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i8 q8, #0x8 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i16 q8, #0x10 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i16 q8, #0x1000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 q8, #0x20 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 q8, #0x2000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 q8, #0x200000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 q8, #0x20000000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 q8, #0x20ff # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i32 q8, #0x20ffff # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.i64 q8, #0xff0000ff0000ffff # CHECK-NEXT: - - - - - - 0.50 0.50 vmvn.i16 d16, #0x10 # CHECK-NEXT: - - - - - - 0.50 0.50 vmvn.i16 d16, #0x1000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmvn.i32 d16, #0x20 # CHECK-NEXT: - - - - - - 0.50 0.50 vmvn.i32 d16, #0x2000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmvn.i32 d16, #0x200000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmvn.i32 d16, #0x20000000 # CHECK-NEXT: - - - - - - 0.50 0.50 vmvn.i32 d16, #0x20ff # CHECK-NEXT: - - - - - - 0.50 0.50 vmvn.i32 d16, #0x20ffff # CHECK-NEXT: - - - - - - - 1.00 vmovl.s8 q8, d16 # CHECK-NEXT: - - - - - - - 1.00 vmovl.s16 q8, d16 # CHECK-NEXT: - - - - - - - 1.00 vmovl.s32 q8, d16 # CHECK-NEXT: - - - - - - - 1.00 vmovl.u8 q8, d16 # CHECK-NEXT: - - - - - - - 1.00 vmovl.u16 q8, d16 # CHECK-NEXT: - - - - - - - 1.00 vmovl.u32 q8, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vmovn.i16 d16, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vmovn.i32 d16, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vmovn.i64 d16, q8 # CHECK-NEXT: - - - - - - - 1.00 vqmovn.s16 d16, q8 # CHECK-NEXT: - - - - - - - 1.00 vqmovn.s32 d16, q8 # CHECK-NEXT: - - - - - - - 1.00 vqmovn.s64 d16, q8 # CHECK-NEXT: - - - - - - - 1.00 vqmovn.u16 d16, q8 # CHECK-NEXT: - - - - - - - 1.00 vqmovn.u32 d16, q8 # CHECK-NEXT: - - - - - - - 1.00 vqmovn.u64 d16, q8 # CHECK-NEXT: - - - - - - - 1.00 vqmovun.s16 d16, q8 # CHECK-NEXT: - - - - - - - 1.00 vqmovun.s32 d16, q8 # CHECK-NEXT: - - - - - - - 1.00 vqmovun.s64 d16, q8 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vmov.s8 r0, d16[1] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vmov.s16 r0, d16[1] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vmov.u8 r0, d16[1] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vmov.u16 r0, d16[1] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vmov.32 r0, d16[1] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmov.8 d16[1], r1 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmov.16 d16[1], r1 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmov.32 d16[1], r1 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmov.8 d18[1], r1 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmov.16 d18[1], r1 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vmov.32 d18[1], r1 # CHECK-NEXT: - - - - - - 1.00 - vmla.i8 d16, d18, d17 # CHECK-NEXT: - - - - - - 1.00 - vmla.i16 d16, d18, d17 # CHECK-NEXT: - - - - - - 1.00 - vmla.i32 d16, d18, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmla.f32 d16, d18, d17 # CHECK-NEXT: - - - - - - 1.00 - vmla.i8 q9, q8, q10 # CHECK-NEXT: - - - - - - 1.00 - vmla.i16 q9, q8, q10 # CHECK-NEXT: - - - - - - 1.00 - vmla.i32 q9, q8, q10 # CHECK-NEXT: - - - - - - 0.50 0.50 vmla.f32 q9, q8, q10 # CHECK-NEXT: - - - - - - 1.00 - vmlal.s8 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmlal.s16 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmlal.s32 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmlal.u8 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmlal.u16 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmlal.u32 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vqdmlal.s16 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vqdmlal.s32 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmls.i8 d16, d18, d17 # CHECK-NEXT: - - - - - - 1.00 - vmls.i16 d16, d18, d17 # CHECK-NEXT: - - - - - - 1.00 - vmls.i32 d16, d18, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmls.f32 d16, d18, d17 # CHECK-NEXT: - - - - - - 1.00 - vmls.i8 q9, q8, q10 # CHECK-NEXT: - - - - - - 1.00 - vmls.i16 q9, q8, q10 # CHECK-NEXT: - - - - - - 1.00 - vmls.i32 q9, q8, q10 # CHECK-NEXT: - - - - - - 0.50 0.50 vmls.f32 q9, q8, q10 # CHECK-NEXT: - - - - - - 1.00 - vmlsl.s8 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmlsl.s16 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmlsl.s32 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmlsl.u8 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmlsl.u16 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmlsl.u32 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vqdmlsl.s16 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vqdmlsl.s32 q8, d19, d18 # CHECK-NEXT: - - - - - - 1.00 - vmul.i8 d16, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vmul.i16 d16, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vmul.i32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vmul.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vmul.i8 q8, q8, q9 # CHECK-NEXT: - - - - - - 1.00 - vmul.i16 q8, q8, q9 # CHECK-NEXT: - - - - - - 1.00 - vmul.i32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vmul.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 1.00 - vmul.p8 d16, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vmul.p8 q8, q8, q9 # CHECK-NEXT: - - - - - - 1.00 - vqdmulh.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vqdmulh.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vqdmulh.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 1.00 - vqdmulh.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 1.00 - vqrdmulh.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vqrdmulh.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vqrdmulh.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 1.00 - vqrdmulh.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 1.00 - vmull.s8 q8, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vmull.s16 q8, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vmull.s32 q8, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vmull.u8 q8, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vmull.u16 q8, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vmull.u32 q8, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vmull.p8 q8, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vqdmull.s16 q8, d16, d17 # CHECK-NEXT: - - - - - - 1.00 - vqdmull.s32 q8, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vneg.s8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vneg.s16 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vneg.s32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vneg.f32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vneg.s8 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vneg.s16 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vneg.s32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vneg.f32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vqneg.s8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vqneg.s16 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vqneg.s32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vqneg.s8 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vqneg.s16 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vqneg.s32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vpadd.i8 d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vpadd.i16 d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vpadd.i32 d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vpadd.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.s8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.s16 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.s32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.u8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.u16 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.u32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.s8 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.s16 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.s32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.u8 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.u16 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vpaddl.u32 q8, q8 # CHECK-NEXT: - - - - - - - 1.00 vpadal.s8 d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vpadal.s16 d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vpadal.s32 d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vpadal.u8 d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vpadal.u16 d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vpadal.u32 d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vpadal.s8 q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vpadal.s16 q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vpadal.s32 q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vpadal.u8 q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vpadal.u16 q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vpadal.u32 q9, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmin.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmin.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmin.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmin.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmin.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmin.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmin.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmax.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmax.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmax.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmax.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmax.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmax.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vpmax.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vrecpe.u32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vrecpe.u32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vrecpe.f32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vrecpe.f32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vrecps.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vrecps.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vrsqrte.u32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vrsqrte.u32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vrsqrte.f32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vrsqrte.f32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vrsqrts.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vrsqrts.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev64.8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev64.16 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev64.32 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev64.8 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev64.16 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev64.32 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev32.8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev32.16 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev32.8 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev32.16 q8, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev16.8 d16, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vrev16.8 q8, q8 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s64 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u64 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s64 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u8 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u16 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u32 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u64 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s8 d16, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s16 d16, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s32 d16, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s64 d16, d16, #63 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u8 d16, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u16 d16, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u32 d16, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u64 d16, d16, #63 # CHECK-NEXT: - - - - - - - 1.00 vqshlu.s8 d16, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vqshlu.s16 d16, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vqshlu.s32 d16, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vqshlu.s64 d16, d16, #63 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s8 q8, q8, #7 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s16 q8, q8, #15 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s32 q8, q8, #31 # CHECK-NEXT: - - - - - - - 1.00 vqshl.s64 q8, q8, #63 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u8 q8, q8, #7 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u16 q8, q8, #15 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u32 q8, q8, #31 # CHECK-NEXT: - - - - - - - 1.00 vqshl.u64 q8, q8, #63 # CHECK-NEXT: - - - - - - - 1.00 vqshlu.s8 q8, q8, #7 # CHECK-NEXT: - - - - - - - 1.00 vqshlu.s16 q8, q8, #15 # CHECK-NEXT: - - - - - - - 1.00 vqshlu.s32 q8, q8, #31 # CHECK-NEXT: - - - - - - - 1.00 vqshlu.s64 q8, q8, #63 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.s64 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.u64 d16, d16, d17 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.s64 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.u8 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.u16 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.u32 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqrshl.u64 q8, q8, q9 # CHECK-NEXT: - - - - - - - 1.00 vqshrn.s16 d16, q8, #8 # CHECK-NEXT: - - - - - - - 1.00 vqshrn.s32 d16, q8, #16 # CHECK-NEXT: - - - - - - - 1.00 vqshrn.s64 d16, q8, #32 # CHECK-NEXT: - - - - - - - 1.00 vqshrn.u16 d16, q8, #8 # CHECK-NEXT: - - - - - - - 1.00 vqshrn.u32 d16, q8, #16 # CHECK-NEXT: - - - - - - - 1.00 vqshrn.u64 d16, q8, #32 # CHECK-NEXT: - - - - - - - 1.00 vqshrun.s16 d16, q8, #8 # CHECK-NEXT: - - - - - - - 1.00 vqshrun.s32 d16, q8, #16 # CHECK-NEXT: - - - - - - - 1.00 vqshrun.s64 d16, q8, #32 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.s16 d16, q8, #8 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.s32 d16, q8, #16 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.s64 d16, q8, #32 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.u16 d16, q8, #8 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.u32 d16, q8, #16 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.u64 d16, q8, #32 # CHECK-NEXT: - - - - - - - 1.00 vqrshrun.s16 d16, q8, #8 # CHECK-NEXT: - - - - - - - 1.00 vqrshrun.s32 d16, q8, #16 # CHECK-NEXT: - - - - - - - 1.00 vqrshrun.s64 d16, q8, #32 # CHECK-NEXT: - - - - - - - 1.00 vshl.u8 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vshl.u16 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vshl.u32 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vshl.u64 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vshl.i8 d16, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vshl.i16 d16, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vshl.i32 d16, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vshl.i64 d16, d16, #63 # CHECK-NEXT: - - - - - - - 1.00 vshl.u8 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vshl.u16 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vshl.u32 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vshl.u64 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vshl.i8 q8, q8, #7 # CHECK-NEXT: - - - - - - - 1.00 vshl.i16 q8, q8, #15 # CHECK-NEXT: - - - - - - - 1.00 vshl.i32 q8, q8, #31 # CHECK-NEXT: - - - - - - - 1.00 vshl.i64 q8, q8, #63 # CHECK-NEXT: - - - - - - - 1.00 vshr.u8 d16, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vshr.u16 d16, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vshr.u32 d16, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vshr.u64 d16, d16, #63 # CHECK-NEXT: - - - - - - - 1.00 vshr.u8 q8, q8, #7 # CHECK-NEXT: - - - - - - - 1.00 vshr.u16 q8, q8, #15 # CHECK-NEXT: - - - - - - - 1.00 vshr.u32 q8, q8, #31 # CHECK-NEXT: - - - - - - - 1.00 vshr.u64 q8, q8, #63 # CHECK-NEXT: - - - - - - - 1.00 vshr.s8 d16, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vshr.s16 d16, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vshr.s32 d16, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vshr.s64 d16, d16, #63 # CHECK-NEXT: - - - - - - - 1.00 vshr.s8 q8, q8, #7 # CHECK-NEXT: - - - - - - - 1.00 vshr.s16 q8, q8, #15 # CHECK-NEXT: - - - - - - - 1.00 vshr.s32 q8, q8, #31 # CHECK-NEXT: - - - - - - - 1.00 vshr.s64 q8, q8, #63 # CHECK-NEXT: - - - - - - - 1.00 vsra.u8 d16, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vsra.u16 d16, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vsra.u32 d16, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vsra.u64 d16, d16, #63 # CHECK-NEXT: - - - - - - - 1.00 vsra.u8 q8, q8, #7 # CHECK-NEXT: - - - - - - - 1.00 vsra.u16 q8, q8, #15 # CHECK-NEXT: - - - - - - - 1.00 vsra.u32 q8, q8, #31 # CHECK-NEXT: - - - - - - - 1.00 vsra.u64 q8, q8, #63 # CHECK-NEXT: - - - - - - - 1.00 vsra.s8 d16, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vsra.s16 d16, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vsra.s32 d16, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vsra.s64 d16, d16, #63 # CHECK-NEXT: - - - - - - - 1.00 vsra.s8 q8, q8, #7 # CHECK-NEXT: - - - - - - - 1.00 vsra.s16 q8, q8, #15 # CHECK-NEXT: - - - - - - - 1.00 vsra.s32 q8, q8, #31 # CHECK-NEXT: - - - - - - - 1.00 vsra.s64 q8, q8, #63 # CHECK-NEXT: - - - - - - - 1.00 vsri.8 d16, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vsri.16 d16, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vsri.32 d16, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vsri.64 d16, d16, #63 # CHECK-NEXT: - - - - - - - 1.00 vsri.8 q8, q8, #7 # CHECK-NEXT: - - - - - - - 1.00 vsri.16 q8, q8, #15 # CHECK-NEXT: - - - - - - - 1.00 vsri.32 q8, q8, #31 # CHECK-NEXT: - - - - - - - 1.00 vsri.64 q8, q8, #63 # CHECK-NEXT: - - - - - - - 1.00 vsli.8 d16, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vsli.16 d16, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vsli.32 d16, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vsli.64 d16, d16, #63 # CHECK-NEXT: - - - - - - - 1.00 vsli.8 q8, q8, #7 # CHECK-NEXT: - - - - - - - 1.00 vsli.16 q8, q8, #15 # CHECK-NEXT: - - - - - - - 1.00 vsli.32 q8, q8, #31 # CHECK-NEXT: - - - - - - - 1.00 vsli.64 q8, q8, #63 # CHECK-NEXT: - - - - - - - 1.00 vshll.s8 q8, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vshll.s16 q8, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vshll.s32 q8, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vshll.u8 q8, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vshll.u16 q8, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vshll.u32 q8, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vshll.i8 q8, d16, #8 # CHECK-NEXT: - - - - - - - 1.00 vshll.i16 q8, d16, #16 # CHECK-NEXT: - - - - - - - 1.00 vshll.i32 q8, d16, #32 # CHECK-NEXT: - - - - - - - 1.00 vshrn.i16 d16, q8, #8 # CHECK-NEXT: - - - - - - - 1.00 vshrn.i32 d16, q8, #16 # CHECK-NEXT: - - - - - - - 1.00 vshrn.i64 d16, q8, #32 # CHECK-NEXT: - - - - - - - 1.00 vrshl.s8 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vrshl.s16 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vrshl.s32 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vrshl.s64 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vrshl.u8 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vrshl.u16 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vrshl.u32 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vrshl.u64 d16, d17, d16 # CHECK-NEXT: - - - - - - - 1.00 vrshl.s8 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vrshl.s16 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vrshl.s32 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vrshl.s64 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vrshl.u8 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vrshl.u16 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vrshl.u32 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vrshl.u64 q8, q9, q8 # CHECK-NEXT: - - - - - - - 1.00 vrshr.s8 d16, d16, #8 # CHECK-NEXT: - - - - - - - 1.00 vrshr.s16 d16, d16, #16 # CHECK-NEXT: - - - - - - - 1.00 vrshr.s32 d16, d16, #32 # CHECK-NEXT: - - - - - - - 1.00 vrshr.s64 d16, d16, #64 # CHECK-NEXT: - - - - - - - 1.00 vrshr.u8 d16, d16, #8 # CHECK-NEXT: - - - - - - - 1.00 vrshr.u16 d16, d16, #16 # CHECK-NEXT: - - - - - - - 1.00 vrshr.u32 d16, d16, #32 # CHECK-NEXT: - - - - - - - 1.00 vrshr.u64 d16, d16, #64 # CHECK-NEXT: - - - - - - - 1.00 vrshr.s8 q8, q8, #8 # CHECK-NEXT: - - - - - - - 1.00 vrshr.s16 q8, q8, #16 # CHECK-NEXT: - - - - - - - 1.00 vrshr.s32 q8, q8, #32 # CHECK-NEXT: - - - - - - - 1.00 vrshr.s64 q8, q8, #64 # CHECK-NEXT: - - - - - - - 1.00 vrshr.u8 q8, q8, #8 # CHECK-NEXT: - - - - - - - 1.00 vrshr.u16 q8, q8, #16 # CHECK-NEXT: - - - - - - - 1.00 vrshr.u32 q8, q8, #32 # CHECK-NEXT: - - - - - - - 1.00 vrshr.u64 q8, q8, #64 # CHECK-NEXT: - - - - - - - 1.00 vrshrn.i16 d16, q8, #8 # CHECK-NEXT: - - - - - - - 1.00 vrshrn.i32 d16, q8, #16 # CHECK-NEXT: - - - - - - - 1.00 vrshrn.i64 d16, q8, #32 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.s16 d16, q8, #4 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.s32 d16, q8, #13 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.s64 d16, q8, #13 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.u16 d16, q8, #4 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.u32 d16, q8, #13 # CHECK-NEXT: - - - - - - - 1.00 vqrshrn.u64 d16, q8, #13 # CHECK-NEXT: - - - - - - - 1.00 vsra.s8 d17, d16, #8 # CHECK-NEXT: - - - - - - - 1.00 vsra.s16 d17, d16, #16 # CHECK-NEXT: - - - - - - - 1.00 vsra.s32 d17, d16, #32 # CHECK-NEXT: - - - - - - - 1.00 vsra.s64 d17, d16, #64 # CHECK-NEXT: - - - - - - - 1.00 vsra.s8 q8, q9, #8 # CHECK-NEXT: - - - - - - - 1.00 vsra.s16 q8, q9, #16 # CHECK-NEXT: - - - - - - - 1.00 vsra.s32 q8, q9, #32 # CHECK-NEXT: - - - - - - - 1.00 vsra.s64 q8, q9, #64 # CHECK-NEXT: - - - - - - - 1.00 vsra.u8 d17, d16, #8 # CHECK-NEXT: - - - - - - - 1.00 vsra.u16 d17, d16, #16 # CHECK-NEXT: - - - - - - - 1.00 vsra.u32 d17, d16, #32 # CHECK-NEXT: - - - - - - - 1.00 vsra.u64 d17, d16, #64 # CHECK-NEXT: - - - - - - - 1.00 vsra.u8 q8, q9, #8 # CHECK-NEXT: - - - - - - - 1.00 vsra.u16 q8, q9, #16 # CHECK-NEXT: - - - - - - - 1.00 vsra.u32 q8, q9, #32 # CHECK-NEXT: - - - - - - - 1.00 vsra.u64 q8, q9, #64 # CHECK-NEXT: - - - - - - - 1.00 vrsra.s8 d17, d16, #8 # CHECK-NEXT: - - - - - - - 1.00 vrsra.s16 d17, d16, #16 # CHECK-NEXT: - - - - - - - 1.00 vrsra.s32 d17, d16, #32 # CHECK-NEXT: - - - - - - - 1.00 vrsra.s64 d17, d16, #64 # CHECK-NEXT: - - - - - - - 1.00 vrsra.u8 d17, d16, #8 # CHECK-NEXT: - - - - - - - 1.00 vrsra.u16 d17, d16, #16 # CHECK-NEXT: - - - - - - - 1.00 vrsra.u32 d17, d16, #32 # CHECK-NEXT: - - - - - - - 1.00 vrsra.u64 d17, d16, #64 # CHECK-NEXT: - - - - - - - 1.00 vrsra.s8 q8, q9, #8 # CHECK-NEXT: - - - - - - - 1.00 vrsra.s16 q8, q9, #16 # CHECK-NEXT: - - - - - - - 1.00 vrsra.s32 q8, q9, #32 # CHECK-NEXT: - - - - - - - 1.00 vrsra.s64 q8, q9, #64 # CHECK-NEXT: - - - - - - - 1.00 vrsra.u8 q8, q9, #8 # CHECK-NEXT: - - - - - - - 1.00 vrsra.u16 q8, q9, #16 # CHECK-NEXT: - - - - - - - 1.00 vrsra.u32 q8, q9, #32 # CHECK-NEXT: - - - - - - - 1.00 vrsra.u64 q8, q9, #64 # CHECK-NEXT: - - - - - - - 1.00 vsli.8 d17, d16, #7 # CHECK-NEXT: - - - - - - - 1.00 vsli.16 d17, d16, #15 # CHECK-NEXT: - - - - - - - 1.00 vsli.32 d17, d16, #31 # CHECK-NEXT: - - - - - - - 1.00 vsli.64 d17, d16, #63 # CHECK-NEXT: - - - - - - - 1.00 vsli.8 q9, q8, #7 # CHECK-NEXT: - - - - - - - 1.00 vsli.16 q9, q8, #15 # CHECK-NEXT: - - - - - - - 1.00 vsli.32 q9, q8, #31 # CHECK-NEXT: - - - - - - - 1.00 vsli.64 q9, q8, #63 # CHECK-NEXT: - - - - - - - 1.00 vsri.8 d17, d16, #8 # CHECK-NEXT: - - - - - - - 1.00 vsri.16 d17, d16, #16 # CHECK-NEXT: - - - - - - - 1.00 vsri.32 d17, d16, #32 # CHECK-NEXT: - - - - - - - 1.00 vsri.64 d17, d16, #64 # CHECK-NEXT: - - - - - - - 1.00 vsri.8 q9, q8, #8 # CHECK-NEXT: - - - - - - - 1.00 vsri.16 q9, q8, #16 # CHECK-NEXT: - - - - - - - 1.00 vsri.32 q9, q8, #32 # CHECK-NEXT: - - - - - - - 1.00 vsri.64 q9, q8, #64 # CHECK-NEXT: - - - - - - 0.50 0.50 vext.8 d16, d17, d16, #3 # CHECK-NEXT: - - - - - - 0.50 0.50 vext.8 d16, d17, d16, #5 # CHECK-NEXT: - - - - - - 0.50 0.50 vext.8 q8, q9, q8, #3 # CHECK-NEXT: - - - - - - 0.50 0.50 vext.8 q8, q9, q8, #7 # CHECK-NEXT: - - - - - - 0.50 0.50 vext.16 d16, d17, d16, #3 # CHECK-NEXT: - - - - - - 0.50 0.50 vext.32 q8, q9, q8, #3 # CHECK-NEXT: - - - - - - 1.00 1.00 vtrn.8 d17, d16 # CHECK-NEXT: - - - - - - 1.00 1.00 vtrn.16 d17, d16 # CHECK-NEXT: - - - - - - 1.00 1.00 vtrn.32 d17, d16 # CHECK-NEXT: - - - - - - 1.00 1.00 vtrn.8 q9, q8 # CHECK-NEXT: - - - - - - 1.00 1.00 vtrn.16 q9, q8 # CHECK-NEXT: - - - - - - 1.00 1.00 vtrn.32 q9, q8 # CHECK-NEXT: - - - - - - 1.00 1.00 vuzp.8 d17, d16 # CHECK-NEXT: - - - - - - 1.00 1.00 vuzp.16 d17, d16 # CHECK-NEXT: - - - - - - 1.00 1.00 vuzp.8 q9, q8 # CHECK-NEXT: - - - - - - 1.00 1.00 vuzp.16 q9, q8 # CHECK-NEXT: - - - - - - 1.00 1.00 vuzp.32 q9, q8 # CHECK-NEXT: - - - - - - 1.00 1.00 vzip.8 d17, d16 # CHECK-NEXT: - - - - - - 1.00 1.00 vzip.16 d17, d16 # CHECK-NEXT: - - - - - - 1.00 1.00 vzip.8 q9, q8 # CHECK-NEXT: - - - - - - 1.00 1.00 vzip.16 q9, q8 # CHECK-NEXT: - - - - - - 1.00 1.00 vzip.32 q9, q8 # CHECK-NEXT: - - - - - - 0.50 0.50 vsub.i8 d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vsub.i16 d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vsub.i32 d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vsub.i64 d16, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vsub.f32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vsub.i8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vsub.i16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vsub.i32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vsub.i64 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vsub.f32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubl.s8 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubl.s16 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubl.s32 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubl.u8 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubl.u16 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubl.u32 q8, d17, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubw.s8 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubw.s16 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubw.s32 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubw.u8 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubw.u16 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubw.u32 q8, q8, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vhsub.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhsub.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhsub.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhsub.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhsub.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhsub.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vhsub.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vhsub.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vhsub.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.s8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.s16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.s32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.s64 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.u8 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.u16 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.u32 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.u64 d16, d16, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.s8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.s16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.s32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.s64 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.u8 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.u16 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.u32 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vqsub.u64 q8, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubhn.i16 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubhn.i32 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vsubhn.i64 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vrsubhn.i16 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vrsubhn.i32 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vrsubhn.i64 d16, q8, q9 # CHECK-NEXT: - - - - - - 0.50 0.50 vtbl.8 d16, {d17}, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vtbl.8 d16, {d16, d17}, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vtbl.8 d16, {d16, d17, d18}, d20 # CHECK-NEXT: - - - - - - 0.50 0.50 vtbl.8 d16, {d16, d17, d18, d19}, d20 # CHECK-NEXT: - - - - - - 0.50 0.50 vtbx.8 d18, {d16}, d17 # CHECK-NEXT: - - - - - - 0.50 0.50 vtbx.8 d19, {d16, d17}, d18 # CHECK-NEXT: - - - - - - 0.50 0.50 vtbx.8 d20, {d16, d17, d18}, d21 # CHECK-NEXT: - - - - - - 0.50 0.50 vtbx.8 d20, {d16, d17, d18, d19}, d21 # CHECK-NEXT: - - - 1.00 - - - - vld1.8 {d16}, [r0:64] # CHECK-NEXT: - - - 1.00 - - - - vld1.16 {d16}, [r0] # CHECK-NEXT: - - - 1.00 - - - - vld1.32 {d16}, [r0] # CHECK-NEXT: - - - 1.00 - - - - vld1.64 {d16}, [r0] # CHECK-NEXT: - - - 1.00 - - - - vld1.8 {d16, d17}, [r0:64] # CHECK-NEXT: - - - 1.00 - - - - vld1.16 {d16, d17}, [r0:128] # CHECK-NEXT: - - - 1.00 - - - - vld1.32 {d16, d17}, [r0] # CHECK-NEXT: - - - 1.00 - - - - vld1.64 {d16, d17}, [r0] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.8 {d16, d17}, [r0:64] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.16 {d16, d17}, [r0:128] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.32 {d16, d17}, [r0] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.8 {d16, d17, d18, d19}, [r0:64] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.16 {d16, d17, d18, d19}, [r0:128] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.32 {d16, d17, d18, d19}, [r0:256] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.8 {d16, d17, d18}, [r0:64] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.16 {d16, d17, d18}, [r0] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.32 {d16, d17, d18}, [r0] # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.8 {d16, d18, d20}, [r0:64]! # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.8 {d17, d19, d21}, [r0:64]! # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.16 {d16, d18, d20}, [r0]! # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.16 {d17, d19, d21}, [r0]! # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.32 {d16, d18, d20}, [r0]! # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.32 {d17, d19, d21}, [r0]! # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.8 {d16, d17, d18, d19}, [r0:64] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.16 {d16, d17, d18, d19}, [r0:128] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.32 {d16, d17, d18, d19}, [r0:256] # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.8 {d16, d18, d20, d22}, [r0:256]! # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.8 {d17, d19, d21, d23}, [r0:256]! # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.16 {d16, d18, d20, d22}, [r0]! # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.16 {d17, d19, d21, d23}, [r0]! # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.32 {d16, d18, d20, d22}, [r0]! # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.32 {d17, d19, d21, d23}, [r0]! # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld1.8 {d16[3]}, [r0] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld1.16 {d16[2]}, [r0:16] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld1.32 {d16[1]}, [r0:32] # CHECK-NEXT: - - - 2.00 - - 1.00 1.00 vld2.8 {d16[1], d17[1]}, [r0:16] # CHECK-NEXT: - - - 2.00 - - 1.00 1.00 vld2.16 {d16[1], d17[1]}, [r0:32] # CHECK-NEXT: - - - 2.00 - - 1.00 1.00 vld2.32 {d16[1], d17[1]}, [r0] # CHECK-NEXT: - - - 2.00 - - 1.00 1.00 vld2.16 {d17[1], d19[1]}, [r0] # CHECK-NEXT: - - - 2.00 - - 1.00 1.00 vld2.32 {d17[0], d19[0]}, [r0:64] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.8 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.16 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.32 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.16 {d16[1], d18[1], d20[1]}, [r0] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.32 {d17[1], d19[1], d21[1]}, [r0] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.8 {d0[], d1[], d2[]}, [r4] # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.8 {d0[], d1[], d2[]}, [r4]! # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.8 {d0[], d2[], d4[]}, [r4], r5 # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.16 {d0[], d2[], d4[]}, [r4] # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.16 {d0[], d1[], d2[]}, [r4]! # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.16 {d0[], d2[], d4[]}, [r4], r5 # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.32 {d0[], d1[], d2[]}, [r4] # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.32 {d0[], d1[], d2[]}, [r4]! # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.32 {d0[], d2[], d4[]}, [r4], r5 # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.8 {d0[], d1[], d2[], d3[]}, [r4] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r5 # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.16 {d0[], d1[], d2[], d3[]}, [r4] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r5 # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.32 {d0[], d1[], d2[], d3[]}, [r4] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r5 # CHECK-NEXT: - - - - - 1.00 - - vst1.8 {d16}, [r0:64] # CHECK-NEXT: - - - - - 1.00 - - vst1.16 {d16}, [r0] # CHECK-NEXT: - - - - - 1.00 - - vst1.32 {d16}, [r0] # CHECK-NEXT: - - - - - 1.00 - - vst1.64 {d16}, [r0] # CHECK-NEXT: - - - - - 1.00 - - vst1.8 {d16, d17}, [r0:64] # CHECK-NEXT: - - - - - 1.00 - - vst1.16 {d16, d17}, [r0:128] # CHECK-NEXT: - - - - - 1.00 - - vst1.32 {d16, d17}, [r0] # CHECK-NEXT: - - - - - 1.00 - - vst1.64 {d16, d17}, [r0] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.8 {d16, d17}, [r0:64] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.16 {d16, d17}, [r0:128] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.32 {d16, d17}, [r0] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.8 {d16, d17, d18, d19}, [r0:64] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.16 {d16, d17, d18, d19}, [r0:128] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.32 {d16, d17, d18, d19}, [r0:256] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.8 {d16, d17, d18}, [r0:64] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.16 {d16, d17, d18}, [r0] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.32 {d16, d17, d18}, [r0] # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.8 {d16, d18, d20}, [r0:64]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.8 {d17, d19, d21}, [r0:64]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.16 {d16, d18, d20}, [r0]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.16 {d17, d19, d21}, [r0]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.32 {d16, d18, d20}, [r0]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.32 {d17, d19, d21}, [r0]! # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.8 {d16, d17, d18, d19}, [r0:64] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.16 {d16, d17, d18, d19}, [r0:128] # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.8 {d16, d18, d20, d22}, [r0:256]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.8 {d17, d19, d21, d23}, [r0:256]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.16 {d16, d18, d20, d22}, [r0]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.16 {d17, d19, d21, d23}, [r0]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.32 {d16, d18, d20, d22}, [r0]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.32 {d17, d19, d21, d23}, [r0]! # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.8 {d16[1], d17[1]}, [r0:16] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.16 {d16[1], d17[1]}, [r0:32] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.32 {d16[1], d17[1]}, [r0] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.16 {d17[1], d19[1]}, [r0] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.32 {d17[0], d19[0]}, [r0:64] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.8 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.16 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.32 {d16[1], d17[1], d18[1]}, [r0] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.16 {d17[2], d19[2], d21[2]}, [r0] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.32 {d16[0], d18[0], d20[0]}, [r0] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld1.8 {d0[]}, [r0], r0 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! # CHECK-NEXT: - - - 2.00 - - - - vmovvs r2, lr, s27, s28 # CHECK-NEXT: - - - 1.00 - - - - vmov s3, s4, r1, r2 # CHECK-NEXT: - - - 1.00 - - - - vmov s2, s3, r1, r2 # CHECK-NEXT: - - - 2.00 - - - - vmov r1, r2, s3, s4 # CHECK-NEXT: - - - 2.00 - - - - vmov r1, r2, s2, s3 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vmov d15, r1, r2 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vmov d16, r1, r2 # CHECK-NEXT: - - - 2.00 - - - - vmov r1, r2, d15 # CHECK-NEXT: - - - 2.00 - - - - vmov r1, r2, d16 # CHECK-NEXT: - - - - - - 0.50 0.50 vcvttmi.f32.f16 s2, s19 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.8 {d23, d24, d25}, [r6:64]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.32 {d22, d23, d24, d25}, [pc:64]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.32 {d26, d27}, [r1:64]! # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.f32 d0, #1.600000e+01 # CHECK-NEXT: - - - - - - 0.50 0.50 vmov.f32 q0, #1.600000e+01 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.8 {d8}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.16 {d8}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.32 {d8}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.64 {d8}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.8 {d8}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.16 {d8}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.32 {d8}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.64 {d8}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.8 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.16 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.32 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.64 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.8 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.16 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.32 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.64 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.8 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.16 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.32 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.64 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.8 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.16 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.32 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.64 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.8 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.16 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.32 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.64 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.8 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.16 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.32 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 - - vst1.64 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.8 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.16 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.32 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.8 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.16 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.32 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.8 {d8, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.16 {d8, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.32 {d8, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.8 {d8, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.16 {d8, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.32 {d8, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.8 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.16 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.32 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.8 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.16 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst3.32 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.8 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.16 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.32 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.8 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.16 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst4.32 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: - - - - - 1.00 - - vst1.16 {d8, d9}, [r4] # CHECK-NEXT: - - - - - 1.00 - - vst1.32 {d8, d9}, [r4] # CHECK-NEXT: - - - - - 1.00 - - vst1.64 {d8, d9}, [r4] # CHECK-NEXT: - - - - - 1.00 - - vst1.8 {d8, d9}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.16 {d8, d9}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.32 {d8, d9}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.8 {d8, d9}, [r4] # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.16 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.16 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.32 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.32 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.8 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 - - 1.00 0.50 0.50 vst2.8 {d8, d9}, [r4], r6 # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.16 {d8, d10}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.32 {d8, d10}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst2.8 {d8, d10}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.8 {d8, d9, d10}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.16 {d8, d9, d10}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.32 {d8, d9, d10}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.8 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.16 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.32 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.8 {d8, d10, d12}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.16 {d8, d10, d12}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst3.32 {d8, d10, d12}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.8 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.16 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: - - - - - 1.00 0.50 0.50 vst4.32 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.8 {d8}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.16 {d8}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.32 {d8}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.64 {d8}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.8 {d8}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.16 {d8}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.32 {d8}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.64 {d8}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.8 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.16 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.32 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.64 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.8 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.16 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.32 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.64 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.8 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.16 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.32 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.64 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.8 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.16 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.32 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.64 {d8, d9, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.8 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.16 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.32 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.64 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.8 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.16 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.32 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - - - vld1.64 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d8, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d8, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d8, d10}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d8, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d8, d10}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d8, d10}, [r4], r6 # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.8 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.16 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.32 {d8, d9, d10}, [r4]! # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.8 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.16 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: - 1.50 1.50 3.00 - - 1.50 1.50 vld3.32 {d8, d10, d12}, [r4], r6 # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.8 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.16 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.32 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.8 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.16 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: - 2.00 2.00 4.00 - - 2.00 2.00 vld4.32 {d8, d10, d12, d14}, [r4], r6 # CHECK-NEXT: - - - 1.00 - - - - vld1.16 {d8, d9}, [r4] # CHECK-NEXT: - - - 1.00 - - - - vld1.32 {d8, d9}, [r4] # CHECK-NEXT: - - - 1.00 - - - - vld1.64 {d8, d9}, [r4] # CHECK-NEXT: - - - 1.00 - - - - vld1.8 {d8, d9}, [r4] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.16 {d8, d9}, [r4] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.32 {d8, d9}, [r4] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.8 {d8, d9}, [r4] # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d8, d9}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d8, d9}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d8, d9}, [r4], r6 # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.16 {d8, d10}, [r4] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.32 {d8, d10}, [r4] # CHECK-NEXT: - - - 1.00 - - 0.50 0.50 vld2.8 {d8, d10}, [r4] # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d8, d9, d10, d11}, [r4]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d8, d9, d10, d11}, [r4], r6 # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.8 {d8, d9, d10}, [r4] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.16 {d8, d9, d10}, [r4] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.32 {d8, d9, d10}, [r4] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.8 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.16 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.32 {d8, d9, d10, d11}, [r4] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.8 {d8, d10, d12}, [r4] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.16 {d8, d10, d12}, [r4] # CHECK-NEXT: - - - 3.00 - - 1.50 1.50 vld3.32 {d8, d10, d12}, [r4] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.8 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.16 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: - - - 4.00 - - 2.00 2.00 vld4.32 {d8, d10, d12, d14}, [r4] # CHECK-NEXT: - - - 2.00 - - 1.00 1.00 vld2.8 {d0[], d1[]}, [r2] # CHECK-NEXT: - - - 2.00 - - 1.00 1.00 vld2.16 {d0[], d1[]}, [r2] # CHECK-NEXT: - - - 2.00 - - 1.00 1.00 vld2.32 {d0[], d1[]}, [r2] # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d0[], d1[]}, [r2]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d0[], d1[]}, [r2]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d0[], d1[]}, [r2]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d0[], d1[]}, [r2], r3 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d0[], d1[]}, [r2], r3 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d0[], d1[]}, [r2], r3 # CHECK-NEXT: - - - 2.00 - - 1.00 1.00 vld2.8 {d0[], d2[]}, [r3] # CHECK-NEXT: - - - 2.00 - - 1.00 1.00 vld2.16 {d0[], d2[]}, [r3] # CHECK-NEXT: - - - 2.00 - - 1.00 1.00 vld2.32 {d0[], d2[]}, [r3] # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d0[], d2[]}, [r3]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d0[], d2[]}, [r3]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d0[], d2[]}, [r3]! # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.8 {d0[], d2[]}, [r3], r4 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.16 {d0[], d2[]}, [r3], r4 # CHECK-NEXT: - 0.50 0.50 1.00 - - 0.50 0.50 vld2.32 {d0[], d2[]}, [r3], r4