# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5

aese	v0.16b, v1.16b
aesmc	v0.16b, v0.16b

aesd	v0.16b, v1.16b
aesimc	v0.16b, v0.16b

# ALL:      Iterations:        100
# ALL-NEXT: Instructions:      400

# M3-NEXT:  Total Cycles:      203
# M4-NEXT:  Total Cycles:      203
# M5-NEXT:  Total Cycles:      403

# ALL-NEXT: Total uOps:        400

# ALL:      Dispatch Width:    6

# M3-NEXT:  uOps Per Cycle:    1.97
# M3-NEXT:  IPC:               1.97

# M4-NEXT:  uOps Per Cycle:    1.97
# M4-NEXT:  IPC:               1.97

# M5-NEXT:  uOps Per Cycle:    0.99
# M5-NEXT:  IPC:               0.99

# ALL-NEXT: Block RThroughput: 2.0

# ALL:      Instruction Info:
# ALL-NEXT: [1]: #uOps
# ALL-NEXT: [2]: Latency
# ALL-NEXT: [3]: RThroughput
# ALL-NEXT: [4]: MayLoad
# ALL-NEXT: [5]: MayStore
# ALL-NEXT: [6]: HasSideEffects (U)

# ALL:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:

# M3-NEXT:   1      1     0.50                        aese	v0.16b, v1.16b
# M3-NEXT:   1      1     0.50                        aesmc	v0.16b, v0.16b
# M3-NEXT:   1      1     0.50                        aesd	v0.16b, v1.16b
# M3-NEXT:   1      1     0.50                        aesimc	v0.16b, v0.16b

# M4-NEXT:   1      1     0.50                        aese	v0.16b, v1.16b
# M4-NEXT:   1      1     0.50                        aesmc	v0.16b, v0.16b
# M4-NEXT:   1      1     0.50                        aesd	v0.16b, v1.16b
# M4-NEXT:   1      1     0.50                        aesimc	v0.16b, v0.16b

# M5-NEXT:   1      2     0.50                        aese	v0.16b, v1.16b
# M5-NEXT:   1      2     0.50                        aesmc	v0.16b, v0.16b
# M5-NEXT:   1      2     0.50                        aesd	v0.16b, v1.16b
# M5-NEXT:   1      2     0.50                        aesimc	v0.16b, v0.16b