# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,SSE2 # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX1 # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512VL # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,AVX512BWVL --- | define <16 x i8> @test_sub_v16i8(<16 x i8> %arg1, <16 x i8> %arg2) { %ret = sub <16 x i8> %arg1, %arg2 ret <16 x i8> %ret } define <8 x i16> @test_sub_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) { %ret = sub <8 x i16> %arg1, %arg2 ret <8 x i16> %ret } define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) { %ret = sub <4 x i32> %arg1, %arg2 ret <4 x i32> %ret } define <2 x i64> @test_sub_v2i64(<2 x i64> %arg1, <2 x i64> %arg2) { %ret = sub <2 x i64> %arg1, %arg2 ret <2 x i64> %ret } ... --- name: test_sub_v16i8 # ALL-LABEL: name: test_sub_v16i8 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } # SSE2: %2:vr128 = PSUBBrr %0, %1 # # AVX1: %2:vr128 = VPSUBBrr %0, %1 # # AVX512VL: %2:vr128 = VPSUBBrr %0, %1 # # AVX512BWVL: %2:vr128x = VPSUBBZ128rr %0, %1 body: | bb.1 (%ir-block.0): liveins: $xmm0, $xmm1 %0(<16 x s8>) = COPY $xmm0 %1(<16 x s8>) = COPY $xmm1 %2(<16 x s8>) = G_SUB %0, %1 $xmm0 = COPY %2(<16 x s8>) RET 0, implicit $xmm0 ... --- name: test_sub_v8i16 # ALL-LABEL: name: test_sub_v8i16 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } # SSE2: %2:vr128 = PSUBWrr %0, %1 # # AVX1: %2:vr128 = VPSUBWrr %0, %1 # # AVX512VL: %2:vr128 = VPSUBWrr %0, %1 # # AVX512BWVL: %2:vr128x = VPSUBWZ128rr %0, %1 body: | bb.1 (%ir-block.0): liveins: $xmm0, $xmm1 %0(<8 x s16>) = COPY $xmm0 %1(<8 x s16>) = COPY $xmm1 %2(<8 x s16>) = G_SUB %0, %1 $xmm0 = COPY %2(<8 x s16>) RET 0, implicit $xmm0 ... --- name: test_sub_v4i32 # ALL-LABEL: name: test_sub_v4i32 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } # SSE2: %2:vr128 = PSUBDrr %0, %1 # # AVX1: %2:vr128 = VPSUBDrr %0, %1 # # AVX512VL: %2:vr128x = VPSUBDZ128rr %0, %1 # # AVX512BWVL: %2:vr128x = VPSUBDZ128rr %0, %1 body: | bb.1 (%ir-block.0): liveins: $xmm0, $xmm1 %0(<4 x s32>) = COPY $xmm0 %1(<4 x s32>) = COPY $xmm1 %2(<4 x s32>) = G_SUB %0, %1 $xmm0 = COPY %2(<4 x s32>) RET 0, implicit $xmm0 ... --- name: test_sub_v2i64 # ALL-LABEL: name: test_sub_v2i64 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } # SSE2: %2:vr128 = PSUBQrr %0, %1 # # AVX1: %2:vr128 = VPSUBQrr %0, %1 # # AVX512VL: %2:vr128x = VPSUBQZ128rr %0, %1 # # AVX512BWVL: %2:vr128x = VPSUBQZ128rr %0, %1 body: | bb.1 (%ir-block.0): liveins: $xmm0, $xmm1 %0(<2 x s64>) = COPY $xmm0 %1(<2 x s64>) = COPY $xmm1 %2(<2 x s64>) = G_SUB %0, %1 $xmm0 = COPY %2(<2 x s64>) RET 0, implicit $xmm0 ...