# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -o - -verify-machineinstrs | FileCheck %s
--- |
  %struct.arm_biquad_casd_df1_inst_q31 = type { i32*, i32*, i32, i32 }

  ; Function Attrs: optsize
  define hidden void @arm_biquad_cascade_df1_q31(%struct.arm_biquad_casd_df1_inst_q31* nocapture readonly %arg, i32* nocapture readonly %arg1, i32* nocapture %arg2, i32 %arg3) #0 {
  bb:
    %i = bitcast %struct.arm_biquad_casd_df1_inst_q31* %arg to i32**
    %i4 = load i32*, i32** %i, align 4
    %i5 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, %struct.arm_biquad_casd_df1_inst_q31* %arg, i32 0, i32 1
    %i6 = load i32*, i32** %i5, align 4
    %i7 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, %struct.arm_biquad_casd_df1_inst_q31* %arg, i32 0, i32 2
    %i8 = load i32, i32* %i7, align 4
    %i9 = sub i32 31, %i8
    %i10 = getelementptr inbounds %struct.arm_biquad_casd_df1_inst_q31, %struct.arm_biquad_casd_df1_inst_q31* %arg, i32 0, i32 3
    %i11 = load i32, i32* %i10, align 4
    br label %bb12

  bb12:                                             ; preds = %bb74, %bb
    %i13 = phi i32* [ %i6, %bb ], [ %i18, %bb74 ]
    %i14 = phi i32* [ %i4, %bb ], [ %i85, %bb74 ]
    %i15 = phi i32* [ %arg1, %bb ], [ %arg2, %bb74 ]
    %i16 = phi i32 [ %i11, %bb ], [ %i89, %bb74 ]
    %i18 = getelementptr inbounds i32, i32* %i13, i32 5
    %i19 = load i32, i32* %i14, align 4
    %i20 = getelementptr inbounds i32, i32* %i14, i32 1
    %i21 = load i32, i32* %i20, align 4
    %i22 = getelementptr inbounds i32, i32* %i14, i32 2
    %i23 = load i32, i32* %i22, align 4
    %i24 = getelementptr inbounds i32, i32* %i14, i32 3
    %i25 = load i32, i32* %i24, align 4
    %i26 = call i1 @llvm.test.set.loop.iterations.i32(i32 %arg3)
    br i1 %i26, label %bb27, label %bb74

  bb27:                                             ; preds = %bb12
    %i28 = getelementptr inbounds i32, i32* %i13, i32 4
    %i29 = load i32, i32* %i28, align 4
    %i30 = getelementptr inbounds i32, i32* %i13, i32 3
    %i31 = load i32, i32* %i30, align 4
    %i32 = getelementptr inbounds i32, i32* %i13, i32 2
    %i33 = load i32, i32* %i32, align 4
    %i34 = getelementptr inbounds i32, i32* %i13, i32 1
    %i35 = load i32, i32* %i34, align 4
    %i36 = load i32, i32* %i13, align 4
    br label %bb37

  bb37:                                             ; preds = %bb37, %bb27
    %lsr.iv = phi i32 [ %lsr.iv.next, %bb37 ], [ %arg3, %bb27 ]
    %i38 = phi i32* [ %i15, %bb27 ], [ %i51, %bb37 ]
    %i39 = phi i32* [ %arg2, %bb27 ], [ %i69, %bb37 ]
    %i40 = phi i32 [ %i25, %bb27 ], [ %i41, %bb37 ]
    %i41 = phi i32 [ %i23, %bb27 ], [ %i68, %bb37 ]
    %i42 = phi i32 [ %i21, %bb27 ], [ %i43, %bb37 ]
    %i43 = phi i32 [ %i19, %bb27 ], [ %i52, %bb37 ]
    %i45 = sext i32 %i29 to i64
    %i46 = sext i32 %i31 to i64
    %i47 = sext i32 %i33 to i64
    %i48 = sext i32 %i35 to i64
    %i49 = sext i32 %i36 to i64
    %i50 = zext i32 %i9 to i64
    %i51 = getelementptr inbounds i32, i32* %i38, i32 1
    %i52 = load i32, i32* %i38, align 4
    %i53 = sext i32 %i52 to i64
    %i54 = mul nsw i64 %i53, %i49
    %i55 = sext i32 %i43 to i64
    %i56 = mul nsw i64 %i55, %i48
    %i57 = sext i32 %i42 to i64
    %i58 = mul nsw i64 %i57, %i47
    %i59 = sext i32 %i41 to i64
    %i60 = mul nsw i64 %i59, %i46
    %i61 = sext i32 %i40 to i64
    %i62 = mul nsw i64 %i61, %i45
    %i63 = add i64 %i58, %i56
    %i64 = add i64 %i63, %i60
    %i65 = add i64 %i64, %i62
    %i66 = add i64 %i65, %i54
    %i67 = ashr i64 %i66, %i50
    %i68 = trunc i64 %i67 to i32
    %i69 = getelementptr inbounds i32, i32* %i39, i32 1
    store i32 %i68, i32* %i39, align 4
    %i70 = call i32 @llvm.loop.decrement.reg.i32(i32 %lsr.iv, i32 1)
    %i71 = icmp ne i32 %i70, 0
    %lsr.iv.next = add i32 %lsr.iv, -1
    br i1 %i71, label %bb37, label %bb72

  bb72:                                             ; preds = %bb37
    %i73 = trunc i64 %i67 to i32
    br label %bb74

  bb74:                                             ; preds = %bb72, %bb12
    %i75 = phi i32 [ %i19, %bb12 ], [ %i52, %bb72 ]
    %i76 = phi i32 [ %i21, %bb12 ], [ %i43, %bb72 ]
    %i77 = phi i32 [ %i23, %bb12 ], [ %i73, %bb72 ]
    %i78 = phi i32 [ %i25, %bb12 ], [ %i41, %bb72 ]
    store i32 %i75, i32* %i14, align 4
    %i79 = bitcast i32* %i14 to i8*
    %i80 = getelementptr inbounds i8, i8* %i79, i32 4
    %i81 = bitcast i8* %i80 to i32*
    store i32 %i76, i32* %i81, align 4
    %i82 = bitcast i32* %i14 to i8*
    %i83 = getelementptr inbounds i8, i8* %i82, i32 8
    %i84 = bitcast i8* %i83 to i32*
    store i32 %i77, i32* %i84, align 4
    %i85 = getelementptr inbounds i32, i32* %i14, i32 4
    %i86 = bitcast i32* %i14 to i8*
    %i87 = getelementptr inbounds i8, i8* %i86, i32 12
    %i88 = bitcast i8* %i87 to i32*
    store i32 %i78, i32* %i88, align 4
    %i89 = add i32 %i16, -1
    %i90 = icmp eq i32 %i89, 0
    br i1 %i90, label %bb91, label %bb12

  bb91:                                             ; preds = %bb74
    ret void
  }

  declare i1 @llvm.test.set.loop.iterations.i32(i32) #1
  declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #1

  attributes #0 = { optsize "target-cpu"="cortex-m55" }
  attributes #1 = { noduplicate nounwind "target-cpu"="cortex-m55" }

...
---
name:            arm_biquad_cascade_df1_q31
alignment:       2
tracksRegLiveness: true
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  stackSize:       76
  offsetAdjustment: 0
  maxAlignment:    4
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -44, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 2, name: '', type: spill-slot, offset: -48, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 3, name: '', type: spill-slot, offset: -52, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 4, name: '', type: spill-slot, offset: -56, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 5, name: '', type: spill-slot, offset: -60, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 6, name: '', type: spill-slot, offset: -64, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 7, name: '', type: spill-slot, offset: -68, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 8, name: '', type: spill-slot, offset: -72, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 9, name: '', type: spill-slot, offset: -76, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 10, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 11, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 12, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 13, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 14, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 15, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 16, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 17, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 18, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: arm_biquad_cascade_df1_q31
  ; CHECK: bb.0.bb:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
  ; CHECK:   $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 36
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r11, -8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r10, -12
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r9, -16
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r8, -20
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -24
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r6, -28
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r5, -32
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -36
  ; CHECK:   $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 76
  ; CHECK:   $r7, $r5 = t2LDRDi8 $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i), (load 4 from %ir.i5)
  ; CHECK:   $r6, $r4 = t2LDRDi8 killed $r0, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i7), (load 4 from %ir.i10)
  ; CHECK:   renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r3 :: (store 4 into %stack.9), (store 4 into %stack.8), (store 4 into %stack.7)
  ; CHECK: bb.1.bb12 (align 4):
  ; CHECK:   successors: %bb.2(0x40000000), %bb.5(0x40000000)
  ; CHECK:   liveins: $r1, $r2, $r3, $r4, $r5, $r7
  ; CHECK:   $r9, $r8 = t2LDRDi8 $r7, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i14), (load 4 from %ir.i20)
  ; CHECK:   renamable $lr = nuw t2ADDri renamable $r5, 20, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   $r6, $r12 = t2LDRDi8 $r7, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i22), (load 4 from %ir.i24)
  ; CHECK:   t2CMPri renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   tBcc %bb.5, 0 /* CC::eq */, killed $cpsr
  ; CHECK:   tB %bb.2, 14 /* CC::al */, $noreg
  ; CHECK: bb.2.bb27:
  ; CHECK:   successors: %bb.3(0x80000000)
  ; CHECK:   liveins: $lr, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12
  ; CHECK:   t2STRDi8 killed $lr, killed $r7, $sp, 12, 14 /* CC::al */, $noreg :: (store 4 into %stack.6), (store 4 into %stack.5)
  ; CHECK:   renamable $r0 = tLDRi renamable $r5, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i13)
  ; CHECK:   renamable $r10 = t2LDRi12 renamable $r5, 16, 14 /* CC::al */, $noreg :: (load 4 from %ir.i28)
  ; CHECK:   tSTRspi killed renamable $r0, $sp, 9, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
  ; CHECK:   renamable $r0 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.i34)
  ; CHECK:   tSTRspi killed renamable $r4, $sp, 5, 14 /* CC::al */, $noreg :: (store 4 into %stack.4)
  ; CHECK:   tSTRspi killed renamable $r0, $sp, 8, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
  ; CHECK:   renamable $r0 = tLDRi renamable $r5, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.i32)
  ; CHECK:   tSTRspi killed renamable $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.2)
  ; CHECK:   renamable $r0 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.i30)
  ; CHECK:   tSTRspi killed renamable $r0, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.3)
  ; CHECK:   $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r3 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.9)
  ; CHECK: bb.3.bb37 (align 4):
  ; CHECK:   successors: %bb.3(0x7c000000), %bb.4(0x04000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r6, $r8, $r9, $r10, $r12
  ; CHECK:   renamable $r4 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load 4 from %stack.1)
  ; CHECK:   $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg
  ; CHECK:   $r5 = tMOVr $r9, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = tMOVr $r0, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r6, renamable $r11 = t2SMULL killed $r9, killed renamable $r4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load 4 from %stack.2)
  ; CHECK:   renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.i38)
  ; CHECK:   dead renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
  ; CHECK:   renamable $r6, renamable $r11 = t2SMLAL killed renamable $r8, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load 4 from %stack.3)
  ; CHECK:   $r8 = tMOVr $r5, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
  ; CHECK:   renamable $r6, renamable $r11 = t2SMLAL killed renamable $r12, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
  ; CHECK:   $r12 = tMOVr $r7, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
  ; CHECK:   early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r3, 14 /* CC::al */, $noreg
  ; CHECK:   early-clobber renamable $r2 = t2STR_POST renamable $r6, killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.i39)
  ; CHECK:   tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
  ; CHECK:   tB %bb.4, 14 /* CC::al */, $noreg
  ; CHECK: bb.4.bb72:
  ; CHECK:   successors: %bb.5(0x80000000)
  ; CHECK:   liveins: $r5, $r6, $r7, $r9
  ; CHECK:   $r12 = tMOVr killed $r7, 14 /* CC::al */, $noreg
  ; CHECK:   $r7, $r4 = t2LDRDi8 $sp, 16, 14 /* CC::al */, $noreg :: (load 4 from %stack.5), (load 4 from %stack.4)
  ; CHECK:   $lr = t2ADDri $sp, 4, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   $r8 = tMOVr killed $r5, 14 /* CC::al */, $noreg
  ; CHECK:   t2LDMIA killed $lr, 14 /* CC::al */, $noreg, def $r2, def $r3, def $lr :: (load 4 from %stack.8), (load 4 from %stack.7), (load 4 from %stack.6)
  ; CHECK: bb.5.bb74:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r2, $r3, $r4, $r6, $r7, $r8, $r9, $r12
  ; CHECK:   t2STRDi8 killed $r9, killed $r8, $r7, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.i14), (store 4 into %ir.i81)
  ; CHECK:   t2STRDi8 killed $r6, killed $r12, $r7, 8, 14 /* CC::al */, $noreg :: (store 4 into %ir.i84), (store 4 into %ir.i88)
  ; CHECK:   renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 16, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4, $cpsr = tSUBi8 killed renamable $r4, 1, 14 /* CC::al */, $noreg
  ; CHECK:   $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
  ; CHECK:   $r1 = tMOVr $r2, 14 /* CC::al */, $noreg
  ; CHECK:   t2IT 0, 4, implicit-def $itstate
  ; CHECK:   $sp = frame-destroy tADDspi $sp, 10, 0 /* CC::eq */, $cpsr, implicit $itstate
  ; CHECK:   $sp = frame-destroy t2LDMIA_RET $sp, 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit $sp, implicit killed $r4, implicit killed $r5, implicit killed $r7, implicit killed $itstate
  ; CHECK:   tB %bb.1, 14 /* CC::al */, $noreg
  bb.0.bb:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr

    $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
    frame-setup CFI_INSTRUCTION def_cfa_offset 36
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r11, -8
    frame-setup CFI_INSTRUCTION offset $r10, -12
    frame-setup CFI_INSTRUCTION offset $r9, -16
    frame-setup CFI_INSTRUCTION offset $r8, -20
    frame-setup CFI_INSTRUCTION offset $r7, -24
    frame-setup CFI_INSTRUCTION offset $r6, -28
    frame-setup CFI_INSTRUCTION offset $r5, -32
    frame-setup CFI_INSTRUCTION offset $r4, -36
    $sp = frame-setup tSUBspi $sp, 10, 14 /* CC::al */, $noreg
    frame-setup CFI_INSTRUCTION def_cfa_offset 76
    $r7, $r5 = t2LDRDi8 $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i), (load 4 from %ir.i5)
    $r6, $r4 = t2LDRDi8 killed $r0, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i7), (load 4 from %ir.i10)
    renamable $r0 = t2RSBri killed renamable $r6, 31, 14 /* CC::al */, $noreg, $noreg
    t2STMIA $sp, 14 /* CC::al */, $noreg, killed $r0, $r2, $r3 :: (store 4 into %stack.9), (store 4 into %stack.8), (store 4 into %stack.7)

  bb.1.bb12 (align 4):
    successors: %bb.2(0x40000000), %bb.5(0x40000000)
    liveins: $r1, $r2, $r3, $r4, $r5, $r7

    $r9, $r8 = t2LDRDi8 $r7, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i14), (load 4 from %ir.i20)
    renamable $lr = nuw t2ADDri renamable $r5, 20, 14 /* CC::al */, $noreg, $noreg
    $r6, $r12 = t2LDRDi8 $r7, 8, 14 /* CC::al */, $noreg :: (load 4 from %ir.i22), (load 4 from %ir.i24)
    t2WhileLoopStart renamable $r3, %bb.5, implicit-def dead $cpsr
    tB %bb.2, 14 /* CC::al */, $noreg

  bb.2.bb27:
    successors: %bb.3(0x80000000)
    liveins: $lr, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r12

    t2STRDi8 killed $lr, killed $r7, $sp, 12, 14 /* CC::al */, $noreg :: (store 4 into %stack.6), (store 4 into %stack.5)
    renamable $r0 = tLDRi renamable $r5, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.i13)
    renamable $r10 = t2LDRi12 renamable $r5, 16, 14 /* CC::al */, $noreg :: (load 4 from %ir.i28)
    tSTRspi killed renamable $r0, $sp, 9, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
    renamable $r0 = tLDRi renamable $r5, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.i34)
    tSTRspi killed renamable $r4, $sp, 5, 14 /* CC::al */, $noreg :: (store 4 into %stack.4)
    tSTRspi killed renamable $r0, $sp, 8, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
    renamable $r0 = tLDRi renamable $r5, 2, 14 /* CC::al */, $noreg :: (load 4 from %ir.i32)
    tSTRspi killed renamable $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.2)
    renamable $r0 = tLDRi killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (load 4 from %ir.i30)
    tSTRspi killed renamable $r0, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.3)
    $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg
    renamable $r3 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.9)

  bb.3.bb37 (align 4):
    successors: %bb.3(0x7c000000), %bb.4(0x04000000)
    liveins: $r0, $r1, $r2, $r3, $r6, $r8, $r9, $r10, $r12

    renamable $r4 = tLDRspi $sp, 8, 14 /* CC::al */, $noreg :: (load 4 from %stack.1)
    $r7 = tMOVr killed $r6, 14 /* CC::al */, $noreg
    $r5 = tMOVr $r9, 14 /* CC::al */, $noreg
    $lr = tMOVr $r0, 14 /* CC::al */, $noreg
    renamable $r6, renamable $r11 = t2SMULL killed $r9, killed renamable $r4, 14 /* CC::al */, $noreg
    renamable $r4 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load 4 from %stack.2)
    renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 1, 14 /* CC::al */, $noreg
    renamable $r9, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.i38)
    renamable $lr = t2LoopDec killed renamable $lr, 1
    renamable $r6, renamable $r11 = t2SMLAL killed renamable $r8, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
    renamable $r4 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load 4 from %stack.3)
    $r8 = tMOVr $r5, 14 /* CC::al */, $noreg
    renamable $r6, renamable $r11 = t2SMLAL renamable $r7, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
    renamable $r4 = tLDRspi $sp, 9, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
    renamable $r6, renamable $r11 = t2SMLAL killed renamable $r12, renamable $r10, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
    $r12 = tMOVr $r7, 14 /* CC::al */, $noreg
    renamable $r6, renamable $r11 = t2SMLAL renamable $r9, killed renamable $r4, killed renamable $r6, killed renamable $r11, 14 /* CC::al */, $noreg
    early-clobber renamable $r6, dead early-clobber renamable $r11 = MVE_ASRLr killed renamable $r6, killed renamable $r11, renamable $r3, 14 /* CC::al */, $noreg
    early-clobber renamable $r2 = t2STR_POST renamable $r6, killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.i39)
    t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr
    tB %bb.4, 14 /* CC::al */, $noreg

  bb.4.bb72:
    successors: %bb.5(0x80000000)
    liveins: $r5, $r6, $r7, $r9

    $r12 = tMOVr killed $r7, 14 /* CC::al */, $noreg
    $r7, $r4 = t2LDRDi8 $sp, 16, 14 /* CC::al */, $noreg :: (load 4 from %stack.5), (load 4 from %stack.4)
    $lr = t2ADDri $sp, 4, 14 /* CC::al */, $noreg, $noreg
    $r8 = tMOVr killed $r5, 14 /* CC::al */, $noreg
    t2LDMIA killed $lr, 14 /* CC::al */, $noreg, def $r2, def $r3, def $lr :: (load 4 from %stack.8), (load 4 from %stack.7), (load 4 from %stack.6)

  bb.5.bb74:
    successors: %bb.1(0x7c000000)
    liveins: $lr, $r2, $r3, $r4, $r6, $r7, $r8, $r9, $r12

    t2STRDi8 killed $r9, killed $r8, $r7, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.i14), (store 4 into %ir.i81)
    t2STRDi8 killed $r6, killed $r12, $r7, 8, 14 /* CC::al */, $noreg :: (store 4 into %ir.i84), (store 4 into %ir.i88)
    renamable $r7, dead $cpsr = nuw tADDi8 killed renamable $r7, 16, 14 /* CC::al */, $noreg
    renamable $r4, $cpsr = tSUBi8 killed renamable $r4, 1, 14 /* CC::al */, $noreg
    $r5 = tMOVr killed $lr, 14 /* CC::al */, $noreg
    $r1 = tMOVr $r2, 14 /* CC::al */, $noreg
    t2IT 0, 4, implicit-def $itstate
    $sp = frame-destroy tADDspi $sp, 10, 0 /* CC::eq */, $cpsr, implicit $itstate
    $sp = frame-destroy t2LDMIA_RET $sp, 0 /* CC::eq */, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit $sp, implicit killed $r4, implicit killed $r5, implicit killed $r7, implicit killed $itstate
    tB %bb.1, 14 /* CC::al */, $noreg

...