# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |

  define void @sqrt_v4f32(<4 x float>* %a, <4 x float>* %c) { entry: ret void }
  define void @sqrt_v2f64(<2 x double>* %a, <2 x double>* %c) { entry: ret void }

...
---
name:            sqrt_v4f32
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; P5600-LABEL: name: sqrt_v4f32
    ; P5600: liveins: $a0, $a1
    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
    ; P5600: [[LOAD:%[0-9]+]]:fprb(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
    ; P5600: [[FSQRT:%[0-9]+]]:fprb(<4 x s32>) = G_FSQRT [[LOAD]]
    ; P5600: G_STORE [[FSQRT]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.c)
    ; P5600: RetRA
    %0:_(p0) = COPY $a0
    %1:_(p0) = COPY $a1
    %2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
    %3:_(<4 x s32>) = G_FSQRT %2
    G_STORE %3(<4 x s32>), %1(p0) :: (store 16 into %ir.c)
    RetRA

...
---
name:            sqrt_v2f64
alignment:       4
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $a0, $a1

    ; P5600-LABEL: name: sqrt_v2f64
    ; P5600: liveins: $a0, $a1
    ; P5600: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
    ; P5600: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
    ; P5600: [[LOAD:%[0-9]+]]:fprb(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.a)
    ; P5600: [[FSQRT:%[0-9]+]]:fprb(<2 x s64>) = G_FSQRT [[LOAD]]
    ; P5600: G_STORE [[FSQRT]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.c)
    ; P5600: RetRA
    %0:_(p0) = COPY $a0
    %1:_(p0) = COPY $a1
    %2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
    %3:_(<2 x s64>) = G_FSQRT %2
    G_STORE %3(<2 x s64>), %1(p0) :: (store 16 into %ir.c)
    RetRA

...