; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK-LABEL: test_0000 ; CHECK: vdelta define <64 x i8> @test_0000(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_0001 ; CHECK: vdelta define <64 x i8> @test_0001(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_0002 ; CHECK: vdelta define <64 x i8> @test_0002(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_0003 ; CHECK: vdelta define <64 x i8> @test_0003(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_0004 ; CHECK: vdelta define <64 x i8> @test_0004(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_0005 ; CHECK: vdelta define <64 x i8> @test_0005(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_0006 ; CHECK: vdelta define <64 x i8> @test_0006(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_0007 ; CHECK: vdelta define <64 x i8> @test_0007(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_0008 ; CHECK: vdelta define <64 x i8> @test_0008(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_0009 ; CHECK: vdelta define <64 x i8> @test_0009(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_000a ; CHECK: vdelta define <64 x i8> @test_000a(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_000b ; CHECK: vdelta define <64 x i8> @test_000b(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_000c ; CHECK: vdelta define <64 x i8> @test_000c(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_000d ; CHECK: vdelta define <64 x i8> @test_000d(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_000e ; CHECK: vdelta define <64 x i8> @test_000e(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } ; CHECK-LABEL: test_000f ; CHECK: vdelta define <64 x i8> @test_000f(<64 x i8> %v0) #0 { %p = shufflevector <64 x i8> %v0, <64 x i8> undef, <64 x i32> ret <64 x i8> %p } attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }