# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s --- | target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64" define void @store_v2p0(<2 x i8*> %v, <2 x i8*>* %ptr) { store <2 x i8*> %v, <2 x i8*>* %ptr ret void } define <2 x i8*> @load_v2p0(<2 x i8*>* %ptr) { %v = load <2 x i8*>, <2 x i8*>* %ptr ret <2 x i8*> %v } ... --- name: store_v2p0 alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true registers: - { id: 0, class: fpr } - { id: 1, class: gpr } - { id: 2, class: fpr } machineFunctionInfo: {} body: | bb.1 (%ir-block.0): liveins: $q0, $x0 ; CHECK-LABEL: name: store_v2p0 ; CHECK: liveins: $q0, $x0 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: STRQui [[COPY]], [[COPY1]], 0 :: (store 16 into %ir.ptr) ; CHECK: RET_ReallyLR %0:fpr(<2 x p0>) = COPY $q0 %1:gpr(p0) = COPY $x0 %2:fpr(<2 x s64>) = G_BITCAST %0(<2 x p0>) G_STORE %2(<2 x s64>), %1(p0) :: (store 16 into %ir.ptr) RET_ReallyLR ... --- name: load_v2p0 alignment: 4 legalized: true regBankSelected: true tracksRegLiveness: true registers: - { id: 0, class: gpr } - { id: 1, class: fpr } - { id: 2, class: fpr } machineFunctionInfo: {} body: | bb.1 (%ir-block.0): liveins: $x0 ; CHECK-LABEL: name: load_v2p0 ; CHECK: liveins: $x0 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16 from %ir.ptr) ; CHECK: $q0 = COPY [[LDRQui]] ; CHECK: RET_ReallyLR implicit $q0 %0:gpr(p0) = COPY $x0 %2:fpr(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr) %1:fpr(<2 x p0>) = G_BITCAST %2(<2 x s64>) $q0 = COPY %1(<2 x p0>) RET_ReallyLR implicit $q0 ...