# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name:            sextload_from_inreg
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$x0' }
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: sextload_from_inreg
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load 1, align 2)
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)
    ; CHECK: $w0 = COPY [[ANYEXT]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %0:_(p0) = COPY $x0
    %1:_(s16) = G_LOAD %0(p0) :: (load 2)
    %2:_(s16) = G_SEXT_INREG %1, 8
    %3:_(s32) = G_ANYEXT %2(s16)
    $w0 = COPY %3(s32)
    RET_ReallyLR implicit $w0

...
---
name:            non_pow_2_inreg
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$x0' }
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: non_pow_2_inreg
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4)
    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 24
    ; CHECK: $w0 = COPY [[SEXT_INREG]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %0:_(p0) = COPY $x0
    %1:_(s32) = G_LOAD %0(p0) :: (load 4)
    %2:_(s32) = G_SEXT_INREG %1, 24
    $w0 = COPY %2(s32)
    RET_ReallyLR implicit $w0

...
---
name:            atomic
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$x0' }
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: atomic
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load acquire 2)
    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s16) = G_SEXT_INREG [[LOAD]], 8
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXT_INREG]](s16)
    ; CHECK: $w0 = COPY [[ANYEXT]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %0:_(p0) = COPY $x0
    %1:_(s16) = G_LOAD %0(p0) :: (load acquire 2)
    %2:_(s16) = G_SEXT_INREG %1, 8
    %3:_(s32) = G_ANYEXT %2(s16)
    $w0 = COPY %3(s32)
    RET_ReallyLR implicit $w0

...
---
name:            volatile
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$x0' }
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: volatile
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (volatile load 2)
    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s16) = G_SEXT_INREG [[LOAD]], 8
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXT_INREG]](s16)
    ; CHECK: $w0 = COPY [[ANYEXT]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %0:_(p0) = COPY $x0
    %1:_(s16) = G_LOAD %0(p0) :: (volatile load 2)
    %2:_(s16) = G_SEXT_INREG %1, 8
    %3:_(s32) = G_ANYEXT %2(s16)
    $w0 = COPY %3(s32)
    RET_ReallyLR implicit $w0

...