# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64 -run-pass=aarch64-postlegalizer-lowering -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -mtriple=aarch64 -global-isel -start-before=aarch64-postlegalizer-lowering -stop-after=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=SELECTED --- name: duplane64 alignment: 4 legalized: true tracksRegLiveness: true body: | bb.1.entry: liveins: $q0 ; CHECK-LABEL: name: duplane64 ; CHECK: liveins: $q0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[DUPLANE64_:%[0-9]+]]:_(<2 x s64>) = G_DUPLANE64 [[COPY]], [[C]](s64) ; CHECK: $q0 = COPY [[DUPLANE64_]](<2 x s64>) ; CHECK: RET_ReallyLR implicit $q0 ; SELECTED-LABEL: name: duplane64 ; SELECTED: liveins: $q0 ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; SELECTED: [[DUPv2i64lane:%[0-9]+]]:fpr128 = DUPv2i64lane [[COPY]], 0 ; SELECTED: $q0 = COPY [[DUPv2i64lane]] ; SELECTED: RET_ReallyLR implicit $q0 %1:_(<2 x s64>) = COPY $q0 %2:_(<2 x s64>) = G_IMPLICIT_DEF %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 ... --- name: duplane32 alignment: 4 legalized: true tracksRegLiveness: true body: | bb.1.entry: liveins: $q0 ; CHECK-LABEL: name: duplane32 ; CHECK: liveins: $q0 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[DUPLANE32_:%[0-9]+]]:_(<4 x s32>) = G_DUPLANE32 [[COPY]], [[C]](s64) ; CHECK: $q0 = COPY [[DUPLANE32_]](<4 x s32>) ; CHECK: RET_ReallyLR implicit $q0 ; SELECTED-LABEL: name: duplane32 ; SELECTED: liveins: $q0 ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; SELECTED: [[DUPv4i32lane:%[0-9]+]]:fpr128 = DUPv4i32lane [[COPY]], 0 ; SELECTED: $q0 = COPY [[DUPv4i32lane]] ; SELECTED: RET_ReallyLR implicit $q0 %1:_(<4 x s32>) = COPY $q0 %2:_(<4 x s32>) = G_IMPLICIT_DEF %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0) $q0 = COPY %4(<4 x s32>) RET_ReallyLR implicit $q0 ... --- name: duplane16 alignment: 4 legalized: true tracksRegLiveness: true body: | bb.1.entry: liveins: $q0 ; CHECK-LABEL: name: duplane16 ; CHECK: liveins: $q0 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[DUPLANE16_:%[0-9]+]]:_(<8 x s16>) = G_DUPLANE16 [[COPY]], [[C]](s64) ; CHECK: $q0 = COPY [[DUPLANE16_]](<8 x s16>) ; CHECK: RET_ReallyLR implicit $q0 ; SELECTED-LABEL: name: duplane16 ; SELECTED: liveins: $q0 ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; SELECTED: [[DUPv8i16lane:%[0-9]+]]:fpr128 = DUPv8i16lane [[COPY]], 0 ; SELECTED: $q0 = COPY [[DUPv8i16lane]] ; SELECTED: RET_ReallyLR implicit $q0 %1:_(<8 x s16>) = COPY $q0 %2:_(<8 x s16>) = G_IMPLICIT_DEF %4:_(<8 x s16>) = G_SHUFFLE_VECTOR %1(<8 x s16>), %2, shufflemask(0, 0, 0, 0, 0, 0, 0, 0) $q0 = COPY %4(<8 x s16>) RET_ReallyLR implicit $q0 ... --- name: duplane8 alignment: 4 legalized: true tracksRegLiveness: true body: | bb.1.entry: liveins: $q0 ; CHECK-LABEL: name: duplane8 ; CHECK: liveins: $q0 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[DUPLANE8_:%[0-9]+]]:_(<16 x s8>) = G_DUPLANE8 [[COPY]], [[C]](s64) ; CHECK: $q0 = COPY [[DUPLANE8_]](<16 x s8>) ; CHECK: RET_ReallyLR implicit $q0 ; SELECTED-LABEL: name: duplane8 ; SELECTED: liveins: $q0 ; SELECTED: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 ; SELECTED: [[DUPv16i8lane:%[0-9]+]]:fpr128 = DUPv16i8lane [[COPY]], 0 ; SELECTED: $q0 = COPY [[DUPv16i8lane]] ; SELECTED: RET_ReallyLR implicit $q0 %1:_(<16 x s8>) = COPY $q0 %2:_(<16 x s8>) = G_IMPLICIT_DEF %4:_(<16 x s8>) = G_SHUFFLE_VECTOR %1(<16 x s8>), %2, shufflemask(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) $q0 = COPY %4(<16 x s8>) RET_ReallyLR implicit $q0 ...