//===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions -----------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file provides Sparc specific target descriptions. // //===----------------------------------------------------------------------===// #include "SparcMCTargetDesc.h" #include "SparcInstPrinter.h" #include "SparcMCAsmInfo.h" #include "SparcTargetStreamer.h" #include "TargetInfo/SparcTargetInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; #define GET_INSTRINFO_MC_DESC #include "SparcGenInstrInfo.inc" #define GET_SUBTARGETINFO_MC_DESC #include "SparcGenSubtargetInfo.inc" #define GET_REGINFO_MC_DESC #include "SparcGenRegisterInfo.inc" static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0); MAI->addInitialFrameState(Inst); return MAI; } static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) { MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 2047); MAI->addInitialFrameState(Inst); return MAI; } static MCInstrInfo *createSparcMCInstrInfo() { MCInstrInfo *X = new MCInstrInfo(); InitSparcMCInstrInfo(X); return X; } static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); InitSparcMCRegisterInfo(X, SP::O7); return X; } static MCSubtargetInfo * createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { if (CPU.empty()) CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8"; return createSparcMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); } static MCTargetStreamer * createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { return new SparcTargetELFStreamer(S); } static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm) { return new SparcTargetAsmStreamer(S, OS); } static MCInstPrinter *createSparcMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) { return new SparcInstPrinter(MAI, MII, MRI); } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn X(getTheSparcTarget(), createSparcMCAsmInfo); RegisterMCAsmInfoFn Y(getTheSparcV9Target(), createSparcV9MCAsmInfo); RegisterMCAsmInfoFn Z(getTheSparcelTarget(), createSparcMCAsmInfo); for (Target *T : {&getTheSparcTarget(), &getTheSparcV9Target(), &getTheSparcelTarget()}) { // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo); // Register the MC register info. TargetRegistry::RegisterMCRegInfo(*T, createSparcMCRegisterInfo); // Register the MC subtarget info. TargetRegistry::RegisterMCSubtargetInfo(*T, createSparcMCSubtargetInfo); // Register the MC Code Emitter. TargetRegistry::RegisterMCCodeEmitter(*T, createSparcMCCodeEmitter); // Register the asm backend. TargetRegistry::RegisterMCAsmBackend(*T, createSparcAsmBackend); // Register the object target streamer. TargetRegistry::RegisterObjectTargetStreamer(*T, createObjectTargetStreamer); // Register the asm streamer. TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer); // Register the MCInstPrinter TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter); } }