# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s --- | target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv8.1m.main" define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) { entry: %start = call i32 @llvm.start.loop.iterations.i32(i32 %N) %scevgep = getelementptr i32, i32* %a, i32 -1 %scevgep4 = getelementptr i32, i32* %c, i32 -1 %scevgep8 = getelementptr i32, i32* %b, i32 -1 br label %for.header for.body: ; preds = %for.header %scevgep11 = getelementptr i32, i32* %lsr.iv9, i32 1 %ld1 = load i32, i32* %scevgep11, align 4 %scevgep7 = getelementptr i32, i32* %lsr.iv5, i32 1 %ld2 = load i32, i32* %scevgep7, align 4 %mul = mul nsw i32 %ld2, %ld1 %scevgep3 = getelementptr i32, i32* %lsr.iv1, i32 1 store i32 %mul, i32* %scevgep3, align 4 %scevgep2 = getelementptr i32, i32* %lsr.iv1, i32 1 %scevgep6 = getelementptr i32, i32* %lsr.iv5, i32 1 %scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 1 %count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1) %cmp = icmp ne i32 %count.next, 0 br i1 %cmp, label %for.header, label %for.cond.cleanup for.cond.cleanup: ; preds = %for.body ret void for.header: ; preds = %for.body, %entry %lsr.iv9 = phi i32* [ %scevgep8, %entry ], [ %scevgep10, %for.body ] %lsr.iv5 = phi i32* [ %scevgep4, %entry ], [ %scevgep6, %for.body ] %lsr.iv1 = phi i32* [ %scevgep, %entry ], [ %scevgep2, %for.body ] %count = phi i32 [ %start, %entry ], [ %count.next, %for.body ] br label %for.body } ; Function Attrs: nounwind declare i32 @llvm.arm.space(i32 immarg, i32) #0 ; Function Attrs: noduplicate nounwind declare i32 @llvm.start.loop.iterations.i32(i32) #1 ; Function Attrs: noduplicate nounwind declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1 attributes #0 = { nounwind } attributes #1 = { noduplicate nounwind } ... --- name: size_limit alignment: 2 exposesReturnsTwice: false legalized: false regBankSelected: false selected: false failedISel: false tracksRegLiveness: true hasWinCFI: false registers: [] liveins: - { reg: '$r0', virtual-reg: '' } - { reg: '$r1', virtual-reg: '' } - { reg: '$r2', virtual-reg: '' } - { reg: '$r3', virtual-reg: '' } frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false hasPatchPoint: false stackSize: 40 offsetAdjustment: 0 maxAlignment: 4 adjustsStack: false hasCalls: false stackProtector: '' maxCallFrameSize: 0 cvBytesOfCalleeSavedRegisters: 0 hasOpaqueSPAdjustment: false hasVAStart: false hasMustTailInVarArgFunc: false localFrameSize: 0 savePoint: '' restorePoint: '' fixedStack: [] stack: - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 1, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 2, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 3, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 4, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 5, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 6, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 7, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4, stack-id: default, callee-saved-register: '', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 8, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } - { id: 9, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } callSites: [] constants: [] machineFunctionInfo: {} body: | ; CHECK-LABEL: name: size_limit ; CHECK: bb.0.entry: ; CHECK: successors: %bb.3(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: $sp = frame-setup tSUBspi $sp, 8, 14 /* CC::al */, $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40 ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg ; CHECK: tSTRspi killed $r1, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) ; CHECK: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.1) ; CHECK: tSTRspi killed $r0, $sp, 5, 14 /* CC::al */, $noreg :: (store 4 into %stack.2) ; CHECK: tSTRspi killed $r3, $sp, 4, 14 /* CC::al */, $noreg :: (store 4 into %stack.3) ; CHECK: tB %bb.3, 14 /* CC::al */, $noreg ; CHECK: bb.1.for.body: ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK: $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg :: (load 4 from %stack.4) ; CHECK: renamable $r1, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep11) ; CHECK: $r2 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load 4 from %stack.5) ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep7) ; CHECK: renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14 /* CC::al */, $noreg ; CHECK: $r3 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg :: (load 4 from %stack.6) ; CHECK: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, killed renamable $r3, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep3) ; CHECK: $r1 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.7) ; CHECK: $lr = tMOVr killed $r1, 14 /* CC::al */, $noreg ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr ; CHECK: $r12 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: tSTRspi killed $r0, $sp, 7, 14 /* CC::al */, $noreg :: (store 4 into %stack.0) ; CHECK: tSTRspi killed $r2, $sp, 6, 14 /* CC::al */, $noreg :: (store 4 into %stack.1) ; CHECK: tSTRspi killed $r3, $sp, 5, 14 /* CC::al */, $noreg :: (store 4 into %stack.2) ; CHECK: t2STRi12 killed $r12, $sp, 16, 14 /* CC::al */, $noreg :: (store 4 into %stack.3) ; CHECK: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg ; CHECK: bb.2.for.cond.cleanup: ; CHECK: $sp = tADDspi $sp, 8, 14 /* CC::al */, $noreg ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc ; CHECK: bb.3.for.header: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: $r0 = tLDRspi $sp, 4, 14 /* CC::al */, $noreg :: (load 4 from %stack.3) ; CHECK: $r1 = tLDRspi $sp, 5, 14 /* CC::al */, $noreg :: (load 4 from %stack.2) ; CHECK: $r2 = tLDRspi $sp, 6, 14 /* CC::al */, $noreg :: (load 4 from %stack.1) ; CHECK: $r3 = tLDRspi $sp, 7, 14 /* CC::al */, $noreg :: (load 4 from %stack.0) ; CHECK: tSTRspi killed $r0, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.7) ; CHECK: tSTRspi killed $r1, $sp, 1, 14 /* CC::al */, $noreg :: (store 4 into %stack.6) ; CHECK: tSTRspi killed $r2, $sp, 2, 14 /* CC::al */, $noreg :: (store 4 into %stack.5) ; CHECK: tSTRspi killed $r3, $sp, 3, 14 /* CC::al */, $noreg :: (store 4 into %stack.4) ; CHECK: tB %bb.1, 14 /* CC::al */, $noreg bb.0.entry: successors: %bb.3(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r7, -8 $sp = frame-setup tSUBspi $sp, 8, 14, $noreg frame-setup CFI_INSTRUCTION def_cfa_offset 40 $lr = t2DoLoopStart renamable $r3 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg tSTRspi killed $r1, $sp, 7, 14, $noreg :: (store 4 into %stack.0) tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1) tSTRspi killed $r0, $sp, 5, 14, $noreg :: (store 4 into %stack.2) tSTRspi killed $r3, $sp, 4, 14, $noreg :: (store 4 into %stack.3) tB %bb.3, 14, $noreg bb.1.for.body: successors: %bb.3(0x40000000), %bb.2(0x40000000) $r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.4) renamable $r1, renamable $r0 = t2LDR_PRE renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep11) $r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.5) renamable $r3, renamable $r2 = t2LDR_PRE renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14, $noreg $r3 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.6) early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, renamable $r3, 4, 14, $noreg :: (store 4 into %ir.scevgep3) $r1 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.7) $lr = tMOVr killed $r1, 14, $noreg renamable $lr = t2LoopDec killed renamable $lr, 1 $r12 = tMOVr $lr, 14, $noreg tSTRspi killed $r0, $sp, 7, 14, $noreg :: (store 4 into %stack.0) tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1) tSTRspi killed $r3, $sp, 5, 14, $noreg :: (store 4 into %stack.2) t2STRi12 killed $r12, $sp, 16, 14, $noreg :: (store 4 into %stack.3) t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr tB %bb.2, 14, $noreg bb.2.for.cond.cleanup: $sp = tADDspi $sp, 8, 14, $noreg tPOP_RET 14, $noreg, def $r7, def $pc bb.3.for.header: successors: %bb.1(0x80000000) $r0 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.3) $r1 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.2) $r2 = tLDRspi $sp, 6, 14, $noreg :: (load 4 from %stack.1) $r3 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0) tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.7) tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6) tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.5) tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store 4 into %stack.4) tB %bb.1, 14, $noreg ...