90 lines
3.1 KiB
C++
90 lines
3.1 KiB
C++
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//===- llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUSubtarget.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetMachine.h"
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#include "gtest/gtest.h"
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#include <thread>
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using namespace llvm;
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std::once_flag flag;
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void InitializeAMDGPUTarget() {
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std::call_once(flag, []() {
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LLVMInitializeAMDGPUTargetInfo();
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LLVMInitializeAMDGPUTarget();
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LLVMInitializeAMDGPUTargetMC();
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});
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}
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std::unique_ptr<const GCNTargetMachine>
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createTargetMachine(std::string TStr, StringRef CPU, StringRef FS) {
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InitializeAMDGPUTarget();
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std::string Error;
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const Target *T = TargetRegistry::lookupTarget(TStr, Error);
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if (!T)
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return nullptr;
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TargetOptions Options;
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return std::unique_ptr<GCNTargetMachine>(static_cast<GCNTargetMachine *>(
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T->createTargetMachine(TStr, CPU, FS, Options, None, None)));
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}
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TEST(AMDGPUDwarfRegMappingTests, TestWave64DwarfRegMapping) {
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for (auto Triple :
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{"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
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auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize64");
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if (TM) {
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GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM);
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auto MRI = ST.getRegisterInfo();
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if (MRI) {
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// Wave64 Dwarf register mapping test numbers
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// PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
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// S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
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// A0 => 3072, A255 => 3327
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for (int llvmReg :
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{16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
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MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
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EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
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}
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}
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}
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}
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}
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TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {
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for (auto Triple :
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{"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
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auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize32");
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if (TM) {
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GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM);
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auto MRI = ST.getRegisterInfo();
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if (MRI) {
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// Wave32 Dwarf register mapping test numbers
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// PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
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// S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
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// A0 => 2048, A255 => 2303
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for (int llvmReg :
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{16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
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MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
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EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
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}
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}
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}
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}
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}
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