53 lines
2.0 KiB
ArmAsm
53 lines
2.0 KiB
ArmAsm
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
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# An instruction that writes to a 32-bit register will not have any false
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# dependence on the corresponding 64-bit register because the upper part of
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# the 64-bit register is set to zero
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imulq %rax, %rcx
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addl %edx, %ecx
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addq %rcx, %rdx
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 3
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# CHECK-NEXT: Total Cycles: 9
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# CHECK-NEXT: Total uOps: 4
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# CHECK: Dispatch Width: 4
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# CHECK-NEXT: uOps Per Cycle: 0.44
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# CHECK-NEXT: IPC: 0.33
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# CHECK-NEXT: Block RThroughput: 1.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 2 4 1.00 imulq %rax, %rcx
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# CHECK-NEXT: 1 1 0.25 addl %edx, %ecx
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# CHECK-NEXT: 1 1 0.25 addq %rcx, %rdx
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# CHECK: Timeline view:
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# CHECK-NEXT: Index 012345678
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# CHECK: [0,0] DeeeeER . imulq %rax, %rcx
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# CHECK-NEXT: [0,1] D====eER. addl %edx, %ecx
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# CHECK-NEXT: [0,2] D=====eER addq %rcx, %rdx
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rcx
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# CHECK-NEXT: 1. 1 5.0 0.0 0.0 addl %edx, %ecx
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# CHECK-NEXT: 2. 1 6.0 0.0 0.0 addq %rcx, %rdx
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# CHECK-NEXT: 1 4.0 0.3 0.0 <total>
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