193 lines
6.4 KiB
LLVM
193 lines
6.4 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512cd | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512cd | FileCheck %s --check-prefixes=CHECK,X64
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declare <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
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define <16 x i32> @test_conflict_d(<16 x i32> %a) {
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; CHECK-LABEL: test_conflict_d:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpconflictd %zmm0, %zmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> undef, i16 -1)
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ret <16 x i32> %res
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}
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define <16 x i32> @test_mask_conflict_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
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; X86-LABEL: test_mask_conflict_d:
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; X86: # %bb.0:
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; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
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; X86-NEXT: vpconflictd %zmm0, %zmm1 {%k1}
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; X86-NEXT: vmovdqa64 %zmm1, %zmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mask_conflict_d:
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; X64: # %bb.0:
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vpconflictd %zmm0, %zmm1 {%k1}
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; X64-NEXT: vmovdqa64 %zmm1, %zmm0
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; X64-NEXT: retq
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%res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
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ret <16 x i32> %res
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}
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define <16 x i32> @test_maskz_conflict_d(<16 x i32> %a, i16 %mask) {
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; X86-LABEL: test_maskz_conflict_d:
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; X86: # %bb.0:
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; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
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; X86-NEXT: vpconflictd %zmm0, %zmm0 {%k1} {z}
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; X86-NEXT: retl
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;
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; X64-LABEL: test_maskz_conflict_d:
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; X64: # %bb.0:
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vpconflictd %zmm0, %zmm0 {%k1} {z}
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; X64-NEXT: retq
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%res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 %mask)
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ret <16 x i32> %res
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}
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declare <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
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define <8 x i64> @test_conflict_q(<8 x i64> %a) {
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; CHECK-LABEL: test_conflict_q:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpconflictq %zmm0, %zmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%res = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a, <8 x i64> undef, i8 -1)
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ret <8 x i64> %res
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}
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define <8 x i64> @test_mask_conflict_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
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; X86-LABEL: test_mask_conflict_q:
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; X86: # %bb.0:
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: kmovw %eax, %k1
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; X86-NEXT: vpconflictq %zmm0, %zmm1 {%k1}
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; X86-NEXT: vmovdqa64 %zmm1, %zmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mask_conflict_q:
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; X64: # %bb.0:
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vpconflictq %zmm0, %zmm1 {%k1}
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; X64-NEXT: vmovdqa64 %zmm1, %zmm0
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; X64-NEXT: retq
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%res = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
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ret <8 x i64> %res
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}
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define <8 x i64> @test_maskz_conflict_q(<8 x i64> %a, i8 %mask) {
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; X86-LABEL: test_maskz_conflict_q:
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; X86: # %bb.0:
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: kmovw %eax, %k1
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; X86-NEXT: vpconflictq %zmm0, %zmm0 {%k1} {z}
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; X86-NEXT: retl
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;
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; X64-LABEL: test_maskz_conflict_q:
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; X64: # %bb.0:
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vpconflictq %zmm0, %zmm0 {%k1} {z}
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; X64-NEXT: retq
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%res = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a, <8 x i64> zeroinitializer, i8 %mask)
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ret <8 x i64> %res
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}
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define <16 x i32> @test_lzcnt_d(<16 x i32> %a) {
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; CHECK-LABEL: test_lzcnt_d:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vplzcntd %zmm0, %zmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%res = call <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 -1)
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ret <16 x i32> %res
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}
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declare <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
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define <8 x i64> @test_lzcnt_q(<8 x i64> %a) {
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; CHECK-LABEL: test_lzcnt_q:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vplzcntq %zmm0, %zmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%res = call <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64> %a, <8 x i64> zeroinitializer, i8 -1)
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ret <8 x i64> %res
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}
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declare <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
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define <16 x i32> @test_mask_lzcnt_d(<16 x i32> %a, <16 x i32> %b, i16 %mask) {
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; X86-LABEL: test_mask_lzcnt_d:
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; X86: # %bb.0:
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; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1
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; X86-NEXT: vplzcntd %zmm0, %zmm1 {%k1}
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; X86-NEXT: vmovdqa64 %zmm1, %zmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mask_lzcnt_d:
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; X64: # %bb.0:
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vplzcntd %zmm0, %zmm1 {%k1}
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; X64-NEXT: vmovdqa64 %zmm1, %zmm0
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; X64-NEXT: retq
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%res = call <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
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ret <16 x i32> %res
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}
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define <8 x i64> @test_mask_lzcnt_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
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; X86-LABEL: test_mask_lzcnt_q:
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; X86: # %bb.0:
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: kmovw %eax, %k1
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; X86-NEXT: vplzcntq %zmm0, %zmm1 {%k1}
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; X86-NEXT: vmovdqa64 %zmm1, %zmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test_mask_lzcnt_q:
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; X64: # %bb.0:
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; X64-NEXT: kmovw %edi, %k1
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; X64-NEXT: vplzcntq %zmm0, %zmm1 {%k1}
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; X64-NEXT: vmovdqa64 %zmm1, %zmm0
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; X64-NEXT: retq
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%res = call <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
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ret <8 x i64> %res
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}
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define <16 x i32> @test_x86_vbroadcastmw_512(i16 %a0) {
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; X86-LABEL: test_x86_vbroadcastmw_512:
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; X86: # %bb.0:
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: vpbroadcastd %eax, %zmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test_x86_vbroadcastmw_512:
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; X64: # %bb.0:
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; X64-NEXT: movzwl %di, %eax
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; X64-NEXT: vpbroadcastd %eax, %zmm0
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; X64-NEXT: retq
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%res = call <16 x i32> @llvm.x86.avx512.broadcastmw.512(i16 %a0)
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ret <16 x i32> %res
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}
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declare <16 x i32> @llvm.x86.avx512.broadcastmw.512(i16)
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define <8 x i64> @test_x86_broadcastmb_512(i8 %a0) {
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; X86-LABEL: test_x86_broadcastmb_512:
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; X86: # %bb.0:
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: vmovd %eax, %xmm0
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; X86-NEXT: vpbroadcastq %xmm0, %zmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test_x86_broadcastmb_512:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: movzbl %dil, %eax
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; X64-NEXT: vpbroadcastq %rax, %zmm0
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; X64-NEXT: retq
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%res = call <8 x i64> @llvm.x86.avx512.broadcastmb.512(i8 %a0)
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ret <8 x i64> %res
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}
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declare <8 x i64> @llvm.x86.avx512.broadcastmb.512(i8)
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