288 lines
11 KiB
LLVM
288 lines
11 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
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; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f \
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; RUN: -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \
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; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all \
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; RUN: -mattr=+f -target-abi ilp32f < %s \
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; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
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; This file contains tests that should have identical output for the ilp32,
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; and ilp32f. As well as calling convention details, we check that
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; ra and fp are consistently stored to fp-4 and fp-8.
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; Check that on RV32 ilp32[f], double is passed in a pair of registers. Unlike
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; the convention for varargs, this need not be an aligned pair.
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define i32 @callee_double_in_regs(i32 %a, double %b) nounwind {
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; RV32I-FPELIM-LABEL: callee_double_in_regs:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: addi sp, sp, -16
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; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-FPELIM-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
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; RV32I-FPELIM-NEXT: mv s0, a0
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; RV32I-FPELIM-NEXT: mv a0, a1
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; RV32I-FPELIM-NEXT: mv a1, a2
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; RV32I-FPELIM-NEXT: call __fixdfsi@plt
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; RV32I-FPELIM-NEXT: add a0, s0, a0
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; RV32I-FPELIM-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
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; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-FPELIM-NEXT: addi sp, sp, 16
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: callee_double_in_regs:
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; RV32I-WITHFP: # %bb.0:
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; RV32I-WITHFP-NEXT: addi sp, sp, -16
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; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: addi s0, sp, 16
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; RV32I-WITHFP-NEXT: mv s1, a0
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; RV32I-WITHFP-NEXT: mv a0, a1
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; RV32I-WITHFP-NEXT: mv a1, a2
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; RV32I-WITHFP-NEXT: call __fixdfsi@plt
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; RV32I-WITHFP-NEXT: add a0, s1, a0
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; RV32I-WITHFP-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: addi sp, sp, 16
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; RV32I-WITHFP-NEXT: ret
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%b_fptosi = fptosi double %b to i32
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%1 = add i32 %a, %b_fptosi
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ret i32 %1
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}
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define i32 @caller_double_in_regs() nounwind {
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; RV32I-FPELIM-LABEL: caller_double_in_regs:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: addi sp, sp, -16
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; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-FPELIM-NEXT: addi a0, zero, 1
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; RV32I-FPELIM-NEXT: lui a2, 262144
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; RV32I-FPELIM-NEXT: mv a1, zero
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; RV32I-FPELIM-NEXT: call callee_double_in_regs@plt
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; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-FPELIM-NEXT: addi sp, sp, 16
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: caller_double_in_regs:
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; RV32I-WITHFP: # %bb.0:
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; RV32I-WITHFP-NEXT: addi sp, sp, -16
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; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: addi s0, sp, 16
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; RV32I-WITHFP-NEXT: addi a0, zero, 1
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; RV32I-WITHFP-NEXT: lui a2, 262144
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; RV32I-WITHFP-NEXT: mv a1, zero
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; RV32I-WITHFP-NEXT: call callee_double_in_regs@plt
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; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: addi sp, sp, 16
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; RV32I-WITHFP-NEXT: ret
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%1 = call i32 @callee_double_in_regs(i32 1, double 2.0)
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ret i32 %1
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}
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; Check 2x*xlen values are aligned appropriately when passed on the stack
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; Must keep define on a single line due to an update_llc_test_checks.py limitation
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define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, double %i, i32 %j, [2 x i32] %k) nounwind {
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; The double should be 8-byte aligned on the stack, but the two-element array
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; should only be 4-byte aligned
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; RV32I-FPELIM-LABEL: callee_aligned_stack:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: lw a0, 0(a2)
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; RV32I-FPELIM-NEXT: lw a1, 20(sp)
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; RV32I-FPELIM-NEXT: lw a2, 0(sp)
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; RV32I-FPELIM-NEXT: lw a3, 8(sp)
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; RV32I-FPELIM-NEXT: lw a4, 16(sp)
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; RV32I-FPELIM-NEXT: add a0, a0, a7
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; RV32I-FPELIM-NEXT: add a0, a0, a2
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; RV32I-FPELIM-NEXT: add a0, a0, a3
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; RV32I-FPELIM-NEXT: add a0, a0, a4
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; RV32I-FPELIM-NEXT: add a0, a0, a1
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: callee_aligned_stack:
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; RV32I-WITHFP: # %bb.0:
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; RV32I-WITHFP-NEXT: addi sp, sp, -16
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; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: addi s0, sp, 16
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; RV32I-WITHFP-NEXT: lw a0, 0(a2)
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; RV32I-WITHFP-NEXT: lw a1, 20(s0)
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; RV32I-WITHFP-NEXT: lw a2, 0(s0)
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; RV32I-WITHFP-NEXT: lw a3, 8(s0)
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; RV32I-WITHFP-NEXT: lw a4, 16(s0)
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; RV32I-WITHFP-NEXT: add a0, a0, a7
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; RV32I-WITHFP-NEXT: add a0, a0, a2
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; RV32I-WITHFP-NEXT: add a0, a0, a3
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; RV32I-WITHFP-NEXT: add a0, a0, a4
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; RV32I-WITHFP-NEXT: add a0, a0, a1
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; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: addi sp, sp, 16
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; RV32I-WITHFP-NEXT: ret
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%1 = bitcast fp128 %c to i128
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%2 = trunc i128 %1 to i32
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%3 = add i32 %2, %g
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%4 = add i32 %3, %h
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%5 = bitcast double %i to i64
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%6 = trunc i64 %5 to i32
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%7 = add i32 %4, %6
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%8 = add i32 %7, %j
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%9 = extractvalue [2 x i32] %k, 0
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%10 = add i32 %8, %9
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ret i32 %10
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}
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define void @caller_aligned_stack() nounwind {
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; The double should be 8-byte aligned on the stack, but the two-element array
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; should only be 4-byte aligned
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; RV32I-FPELIM-LABEL: caller_aligned_stack:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: addi sp, sp, -64
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; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; RV32I-FPELIM-NEXT: addi a0, zero, 18
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; RV32I-FPELIM-NEXT: sw a0, 24(sp)
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; RV32I-FPELIM-NEXT: addi a0, zero, 17
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; RV32I-FPELIM-NEXT: sw a0, 20(sp)
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; RV32I-FPELIM-NEXT: addi a0, zero, 16
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; RV32I-FPELIM-NEXT: sw a0, 16(sp)
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; RV32I-FPELIM-NEXT: lui a0, 262236
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; RV32I-FPELIM-NEXT: addi a0, a0, 655
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; RV32I-FPELIM-NEXT: sw a0, 12(sp)
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; RV32I-FPELIM-NEXT: lui a0, 377487
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; RV32I-FPELIM-NEXT: addi a0, a0, 1475
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; RV32I-FPELIM-NEXT: sw a0, 8(sp)
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; RV32I-FPELIM-NEXT: addi a0, zero, 15
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; RV32I-FPELIM-NEXT: sw a0, 0(sp)
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; RV32I-FPELIM-NEXT: lui a0, 262153
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; RV32I-FPELIM-NEXT: addi a0, a0, 491
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; RV32I-FPELIM-NEXT: sw a0, 44(sp)
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; RV32I-FPELIM-NEXT: lui a0, 545260
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; RV32I-FPELIM-NEXT: addi a0, a0, -1967
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; RV32I-FPELIM-NEXT: sw a0, 40(sp)
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; RV32I-FPELIM-NEXT: lui a0, 964690
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; RV32I-FPELIM-NEXT: addi a0, a0, -328
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; RV32I-FPELIM-NEXT: sw a0, 36(sp)
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; RV32I-FPELIM-NEXT: lui a0, 335544
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; RV32I-FPELIM-NEXT: addi t0, a0, 1311
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; RV32I-FPELIM-NEXT: lui a0, 688509
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; RV32I-FPELIM-NEXT: addi a5, a0, -2048
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; RV32I-FPELIM-NEXT: addi a0, zero, 1
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; RV32I-FPELIM-NEXT: addi a1, zero, 11
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; RV32I-FPELIM-NEXT: addi a2, sp, 32
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; RV32I-FPELIM-NEXT: addi a3, zero, 12
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; RV32I-FPELIM-NEXT: addi a4, zero, 13
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; RV32I-FPELIM-NEXT: addi a6, zero, 4
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; RV32I-FPELIM-NEXT: addi a7, zero, 14
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; RV32I-FPELIM-NEXT: sw t0, 32(sp)
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; RV32I-FPELIM-NEXT: call callee_aligned_stack@plt
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; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; RV32I-FPELIM-NEXT: addi sp, sp, 64
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: caller_aligned_stack:
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; RV32I-WITHFP: # %bb.0:
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; RV32I-WITHFP-NEXT: addi sp, sp, -64
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; RV32I-WITHFP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: addi s0, sp, 64
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; RV32I-WITHFP-NEXT: addi a0, zero, 18
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; RV32I-WITHFP-NEXT: sw a0, 24(sp)
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; RV32I-WITHFP-NEXT: addi a0, zero, 17
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; RV32I-WITHFP-NEXT: sw a0, 20(sp)
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; RV32I-WITHFP-NEXT: addi a0, zero, 16
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; RV32I-WITHFP-NEXT: sw a0, 16(sp)
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; RV32I-WITHFP-NEXT: lui a0, 262236
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; RV32I-WITHFP-NEXT: addi a0, a0, 655
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; RV32I-WITHFP-NEXT: sw a0, 12(sp)
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; RV32I-WITHFP-NEXT: lui a0, 377487
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; RV32I-WITHFP-NEXT: addi a0, a0, 1475
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; RV32I-WITHFP-NEXT: sw a0, 8(sp)
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; RV32I-WITHFP-NEXT: addi a0, zero, 15
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; RV32I-WITHFP-NEXT: sw a0, 0(sp)
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; RV32I-WITHFP-NEXT: lui a0, 262153
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; RV32I-WITHFP-NEXT: addi a0, a0, 491
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; RV32I-WITHFP-NEXT: sw a0, -20(s0)
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; RV32I-WITHFP-NEXT: lui a0, 545260
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; RV32I-WITHFP-NEXT: addi a0, a0, -1967
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; RV32I-WITHFP-NEXT: sw a0, -24(s0)
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; RV32I-WITHFP-NEXT: lui a0, 964690
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; RV32I-WITHFP-NEXT: addi a0, a0, -328
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; RV32I-WITHFP-NEXT: sw a0, -28(s0)
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; RV32I-WITHFP-NEXT: lui a0, 335544
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; RV32I-WITHFP-NEXT: addi t0, a0, 1311
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; RV32I-WITHFP-NEXT: lui a0, 688509
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; RV32I-WITHFP-NEXT: addi a5, a0, -2048
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; RV32I-WITHFP-NEXT: addi a0, zero, 1
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; RV32I-WITHFP-NEXT: addi a1, zero, 11
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; RV32I-WITHFP-NEXT: addi a2, s0, -32
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; RV32I-WITHFP-NEXT: addi a3, zero, 12
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; RV32I-WITHFP-NEXT: addi a4, zero, 13
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; RV32I-WITHFP-NEXT: addi a6, zero, 4
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; RV32I-WITHFP-NEXT: addi a7, zero, 14
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; RV32I-WITHFP-NEXT: sw t0, -32(s0)
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; RV32I-WITHFP-NEXT: call callee_aligned_stack@plt
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; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: addi sp, sp, 64
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; RV32I-WITHFP-NEXT: ret
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%1 = call i32 @callee_aligned_stack(i32 1, i32 11,
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fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
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i64 20000000000, i32 14, i32 15, double 2.720000e+00, i32 16,
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[2 x i32] [i32 17, i32 18])
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ret void
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}
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define double @callee_small_scalar_ret() nounwind {
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; RV32I-FPELIM-LABEL: callee_small_scalar_ret:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: lui a1, 261888
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; RV32I-FPELIM-NEXT: mv a0, zero
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: callee_small_scalar_ret:
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; RV32I-WITHFP: # %bb.0:
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; RV32I-WITHFP-NEXT: addi sp, sp, -16
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; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
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; RV32I-WITHFP-NEXT: addi s0, sp, 16
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; RV32I-WITHFP-NEXT: lui a1, 261888
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; RV32I-WITHFP-NEXT: mv a0, zero
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; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
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; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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|
|
; RV32I-WITHFP-NEXT: addi sp, sp, 16
|
||
|
|
; RV32I-WITHFP-NEXT: ret
|
||
|
|
ret double 1.0
|
||
|
|
}
|
||
|
|
|
||
|
|
define i64 @caller_small_scalar_ret() nounwind {
|
||
|
|
; RV32I-FPELIM-LABEL: caller_small_scalar_ret:
|
||
|
|
; RV32I-FPELIM: # %bb.0:
|
||
|
|
; RV32I-FPELIM-NEXT: addi sp, sp, -16
|
||
|
|
; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||
|
|
; RV32I-FPELIM-NEXT: call callee_small_scalar_ret@plt
|
||
|
|
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||
|
|
; RV32I-FPELIM-NEXT: addi sp, sp, 16
|
||
|
|
; RV32I-FPELIM-NEXT: ret
|
||
|
|
;
|
||
|
|
; RV32I-WITHFP-LABEL: caller_small_scalar_ret:
|
||
|
|
; RV32I-WITHFP: # %bb.0:
|
||
|
|
; RV32I-WITHFP-NEXT: addi sp, sp, -16
|
||
|
|
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||
|
|
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
|
||
|
|
; RV32I-WITHFP-NEXT: addi s0, sp, 16
|
||
|
|
; RV32I-WITHFP-NEXT: call callee_small_scalar_ret@plt
|
||
|
|
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
|
||
|
|
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||
|
|
; RV32I-WITHFP-NEXT: addi sp, sp, 16
|
||
|
|
; RV32I-WITHFP-NEXT: ret
|
||
|
|
%1 = call double @callee_small_scalar_ret()
|
||
|
|
%2 = bitcast double %1 to i64
|
||
|
|
ret i64 %2
|
||
|
|
}
|