35 lines
1017 B
LLVM
35 lines
1017 B
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Test that V_vzero and W_vzero intrinsics work. The W_vzero intrinsic was added
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; for v65/hvx.
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; CHECK-LABEL: f0:
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; CHECK: [[VREG1:v([0-9]+)]] = vxor([[VREG1]],[[VREG1]])
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define void @f0(i16** nocapture %a0) #0 {
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b0:
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%v0 = bitcast i16** %a0 to <16 x i32>*
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%v1 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
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store <16 x i32> %v1, <16 x i32>* %v0, align 64
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vd0() #1
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; CHECK-LABEL: f1:
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; CHECK: [[VREG2:v([0-9]+):([0-9]+).w]] = vsub([[VREG2]],[[VREG2]])
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define void @f1(i16** nocapture %a0) #0 {
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b0:
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%v0 = bitcast i16** %a0 to <32 x i32>*
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%v1 = tail call <32 x i32> @llvm.hexagon.V6.vdd0()
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store <32 x i32> %v1, <32 x i32>* %v0, align 128
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vdd0() #1
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attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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