262 lines
6.4 KiB
LLVM
262 lines
6.4 KiB
LLVM
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap %s --check-prefixes=SI,FUNC,GCN
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap %s --check-prefixes=FUNC,GCN
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap %s --check-prefixes=EG,FUNC
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declare float @llvm.fabs.f32(float) #1
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; FUNC-LABEL: {{^}}fp_to_sint_i32:
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI: v_cvt_i32_f32_e32
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; SI: s_endpgm
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define amdgpu_kernel void @fp_to_sint_i32(i32 addrspace(1)* %out, float %in) {
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%conv = fptosi float %in to i32
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store i32 %conv, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_sint_i32_fabs:
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; SI: v_cvt_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
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define amdgpu_kernel void @fp_to_sint_i32_fabs(i32 addrspace(1)* %out, float %in) {
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%in.fabs = call float @llvm.fabs.f32(float %in)
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%conv = fptosi float %in.fabs to i32
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store i32 %conv, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_sint_v2i32:
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI: v_cvt_i32_f32_e32
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; SI: v_cvt_i32_f32_e32
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define amdgpu_kernel void @fp_to_sint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
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%result = fptosi <2 x float> %in to <2 x i32>
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_sint_v4i32:
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW]}}
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; EG: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
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; SI: v_cvt_i32_f32_e32
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; SI: v_cvt_i32_f32_e32
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; SI: v_cvt_i32_f32_e32
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; SI: v_cvt_i32_f32_e32
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define amdgpu_kernel void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%value = load <4 x float>, <4 x float> addrspace(1) * %in
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%result = fptosi <4 x float> %value to <4 x i32>
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_sint_i64:
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; Check that the compiler doesn't crash with a "cannot select" error
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; SI: s_endpgm
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define amdgpu_kernel void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) {
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entry:
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%0 = fptosi float %in to i64
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store i64 %0, i64 addrspace(1)* %out
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ret void
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}
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; FUNC: {{^}}fp_to_sint_v2i64:
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; SI: s_endpgm
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define amdgpu_kernel void @fp_to_sint_v2i64(<2 x i64> addrspace(1)* %out, <2 x float> %x) {
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%conv = fptosi <2 x float> %x to <2 x i64>
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store <2 x i64> %conv, <2 x i64> addrspace(1)* %out
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ret void
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}
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; FUNC: {{^}}fp_to_sint_v4i64:
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: AND_INT
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; EG-DAG: LSHR
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; EG-DAG: SUB_INT
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; EG-DAG: AND_INT
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; EG-DAG: ASHR
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; EG-DAG: AND_INT
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; EG-DAG: OR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: LSHL
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; EG-DAG: LSHL
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; EG-DAG: SUB_INT
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; EG-DAG: LSHR
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; EG-DAG: LSHR
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; EG-DAG: SETGT_UINT
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; EG-DAG: SETGT_INT
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; EG-DAG: XOR_INT
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; EG-DAG: XOR_INT
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; EG-DAG: SUB_INT
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; EG-DAG: SUB_INT
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; EG-DAG: CNDE_INT
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; EG-DAG: CNDE_INT
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; SI: s_endpgm
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define amdgpu_kernel void @fp_to_sint_v4i64(<4 x i64> addrspace(1)* %out, <4 x float> %x) {
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%conv = fptosi <4 x float> %x to <4 x i64>
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store <4 x i64> %conv, <4 x i64> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_uint_f32_to_i1:
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; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, s{{[0-9]+}}
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; EG: AND_INT
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; EG: SETE_DX10 {{[*]?}} T{{[0-9]+}}.{{[XYZW]}}, KC0[2].Z, literal.y,
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; EG-NEXT: -1082130432(-1.000000e+00)
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define amdgpu_kernel void @fp_to_uint_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
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%conv = fptosi float %in to i1
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store i1 %conv, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_uint_fabs_f32_to_i1:
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; SI: v_cmp_eq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, |s{{[0-9]+}}|
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define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, float %in) #0 {
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%in.fabs = call float @llvm.fabs.f32(float %in)
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%conv = fptosi float %in.fabs to i1
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store i1 %conv, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fp_to_sint_f32_i16:
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; GCN: v_cvt_i32_f32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
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; GCN: buffer_store_short [[VAL]]
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define amdgpu_kernel void @fp_to_sint_f32_i16(i16 addrspace(1)* %out, float %in) #0 {
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%sint = fptosi float %in to i16
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store i16 %sint, i16 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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