605 lines
21 KiB
C++
605 lines
21 KiB
C++
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//===- MipsLegalizerInfo.cpp ------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for Mips.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "MipsLegalizerInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/IR/IntrinsicsMips.h"
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using namespace llvm;
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struct TypesAndMemOps {
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LLT ValTy;
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LLT PtrTy;
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unsigned MemSize;
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bool SystemSupportsUnalignedAccess;
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};
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// Assumes power of 2 memory size. Subtargets that have only naturally-aligned
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// memory access need to perform additional legalization here.
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static bool isUnalignedMemmoryAccess(uint64_t MemSize, uint64_t AlignInBits) {
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assert(isPowerOf2_64(MemSize) && "Expected power of 2 memory size");
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assert(isPowerOf2_64(AlignInBits) && "Expected power of 2 align");
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if (MemSize > AlignInBits)
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return true;
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return false;
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}
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static bool
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CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query,
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std::initializer_list<TypesAndMemOps> SupportedValues) {
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unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits;
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// Non power of two memory access is never legal.
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if (!isPowerOf2_64(QueryMemSize))
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return false;
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for (auto &Val : SupportedValues) {
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if (Val.ValTy != Query.Types[0])
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continue;
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if (Val.PtrTy != Query.Types[1])
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continue;
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if (Val.MemSize != QueryMemSize)
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continue;
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if (!Val.SystemSupportsUnalignedAccess &&
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isUnalignedMemmoryAccess(QueryMemSize, Query.MMODescrs[0].AlignInBits))
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return false;
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return true;
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}
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return false;
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}
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static bool CheckTyN(unsigned N, const LegalityQuery &Query,
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std::initializer_list<LLT> SupportedValues) {
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for (auto &Val : SupportedValues)
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if (Val == Query.Types[N])
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return true;
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return false;
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}
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MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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using namespace TargetOpcode;
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const LLT s1 = LLT::scalar(1);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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const LLT v16s8 = LLT::vector(16, 8);
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const LLT v8s16 = LLT::vector(8, 16);
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const LLT v4s32 = LLT::vector(4, 32);
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const LLT v2s64 = LLT::vector(2, 64);
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const LLT p0 = LLT::pointer(0, 32);
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getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
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.legalIf([=, &ST](const LegalityQuery &Query) {
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if (CheckTyN(0, Query, {s32}))
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return true;
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if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
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return true;
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return false;
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})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
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.lowerFor({{s32, s1}});
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getActionDefinitionsBuilder(G_UMULH)
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.legalFor({s32})
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.maxScalar(0, s32);
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// MIPS32r6 does not have alignment restrictions for memory access.
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// For MIPS32r5 and older memory access must be naturally-aligned i.e. aligned
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// to at least a multiple of its own size. There is however a two instruction
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// combination that performs 4 byte unaligned access (lwr/lwl and swl/swr)
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// therefore 4 byte load and store are legal and will use NoAlignRequirements.
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bool NoAlignRequirements = true;
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getActionDefinitionsBuilder({G_LOAD, G_STORE})
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.legalIf([=, &ST](const LegalityQuery &Query) {
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if (CheckTy0Ty1MemSizeAlign(
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Query, {{s32, p0, 8, NoAlignRequirements},
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{s32, p0, 16, ST.systemSupportsUnalignedAccess()},
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{s32, p0, 32, NoAlignRequirements},
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{p0, p0, 32, NoAlignRequirements},
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{s64, p0, 64, ST.systemSupportsUnalignedAccess()}}))
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return true;
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if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign(
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Query, {{v16s8, p0, 128, NoAlignRequirements},
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{v8s16, p0, 128, NoAlignRequirements},
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{v4s32, p0, 128, NoAlignRequirements},
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{v2s64, p0, 128, NoAlignRequirements}}))
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return true;
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return false;
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})
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// Custom lower scalar memory access, up to 8 bytes, for:
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// - non-power-of-2 MemSizes
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// - unaligned 2 or 8 byte MemSizes for MIPS32r5 and older
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.customIf([=, &ST](const LegalityQuery &Query) {
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if (!Query.Types[0].isScalar() || Query.Types[1] != p0 ||
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Query.Types[0] == s1)
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return false;
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unsigned Size = Query.Types[0].getSizeInBits();
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unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits;
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assert(QueryMemSize <= Size && "Scalar can't hold MemSize");
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if (Size > 64 || QueryMemSize > 64)
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return false;
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if (!isPowerOf2_64(Query.MMODescrs[0].SizeInBits))
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return true;
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if (!ST.systemSupportsUnalignedAccess() &&
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isUnalignedMemmoryAccess(QueryMemSize,
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Query.MMODescrs[0].AlignInBits)) {
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assert(QueryMemSize != 32 && "4 byte load and store are legal");
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return true;
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}
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return false;
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})
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_IMPLICIT_DEF)
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.legalFor({s32, s64});
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getActionDefinitionsBuilder(G_UNMERGE_VALUES)
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.legalFor({{s32, s64}});
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getActionDefinitionsBuilder(G_MERGE_VALUES)
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.legalFor({{s64, s32}});
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getActionDefinitionsBuilder({G_ZEXTLOAD, G_SEXTLOAD})
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.legalForTypesWithMemDesc({{s32, p0, 8, 8},
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{s32, p0, 16, 8}})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
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.legalIf([](const LegalityQuery &Query) { return false; })
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.maxScalar(0, s32);
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getActionDefinitionsBuilder(G_TRUNC)
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.legalIf([](const LegalityQuery &Query) { return false; })
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.maxScalar(1, s32);
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getActionDefinitionsBuilder(G_SELECT)
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.legalForCartesianProduct({p0, s32, s64}, {s32})
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.minScalar(0, s32)
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.minScalar(1, s32);
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getActionDefinitionsBuilder(G_BRCOND)
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.legalFor({s32})
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_BRJT)
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.legalFor({{p0, s32}});
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getActionDefinitionsBuilder(G_BRINDIRECT)
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.legalFor({p0});
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getActionDefinitionsBuilder(G_PHI)
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.legalFor({p0, s32, s64})
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.minScalar(0, s32);
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getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_SDIV, G_SREM, G_UDIV, G_UREM})
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.legalIf([=, &ST](const LegalityQuery &Query) {
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if (CheckTyN(0, Query, {s32}))
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return true;
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if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
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return true;
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return false;
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})
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.minScalar(0, s32)
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.libcallFor({s64});
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getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
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.legalFor({{s32, s32}})
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.clampScalar(1, s32, s32)
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder(G_ICMP)
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.legalForCartesianProduct({s32}, {s32, p0})
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.clampScalar(1, s32, s32)
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_CONSTANT)
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_PTR_ADD, G_INTTOPTR})
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.legalFor({{p0, s32}});
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getActionDefinitionsBuilder(G_PTRTOINT)
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.legalFor({{s32, p0}});
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getActionDefinitionsBuilder(G_FRAME_INDEX)
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.legalFor({p0});
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getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE})
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.legalFor({p0});
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getActionDefinitionsBuilder(G_DYN_STACKALLOC)
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.lowerFor({{p0, s32}});
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getActionDefinitionsBuilder(G_VASTART)
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.legalFor({p0});
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getActionDefinitionsBuilder(G_BSWAP)
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.legalIf([=, &ST](const LegalityQuery &Query) {
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if (ST.hasMips32r2() && CheckTyN(0, Query, {s32}))
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return true;
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return false;
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})
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.lowerIf([=, &ST](const LegalityQuery &Query) {
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if (!ST.hasMips32r2() && CheckTyN(0, Query, {s32}))
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return true;
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return false;
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})
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.maxScalar(0, s32);
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getActionDefinitionsBuilder(G_BITREVERSE)
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.lowerFor({s32})
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.maxScalar(0, s32);
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getActionDefinitionsBuilder(G_CTLZ)
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.legalFor({{s32, s32}})
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.maxScalar(0, s32)
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.maxScalar(1, s32);
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getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF)
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.lowerFor({{s32, s32}});
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getActionDefinitionsBuilder(G_CTTZ)
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.lowerFor({{s32, s32}})
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.maxScalar(0, s32)
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.maxScalar(1, s32);
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getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF)
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.lowerFor({{s32, s32}, {s64, s64}});
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getActionDefinitionsBuilder(G_CTPOP)
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.lowerFor({{s32, s32}})
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.clampScalar(0, s32, s32)
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.clampScalar(1, s32, s32);
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// FP instructions
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({s32, s64});
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getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT})
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.legalIf([=, &ST](const LegalityQuery &Query) {
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if (CheckTyN(0, Query, {s32, s64}))
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return true;
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if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
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return true;
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return false;
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});
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getActionDefinitionsBuilder(G_FCMP)
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.legalFor({{s32, s32}, {s32, s64}})
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.minScalar(0, s32);
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getActionDefinitionsBuilder({G_FCEIL, G_FFLOOR})
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.libcallFor({s32, s64});
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getActionDefinitionsBuilder(G_FPEXT)
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.legalFor({{s64, s32}});
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getActionDefinitionsBuilder(G_FPTRUNC)
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.legalFor({{s32, s64}});
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// FP to int conversion instructions
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getActionDefinitionsBuilder(G_FPTOSI)
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.legalForCartesianProduct({s32}, {s64, s32})
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.libcallForCartesianProduct({s64}, {s64, s32})
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_FPTOUI)
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.libcallForCartesianProduct({s64}, {s64, s32})
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.lowerForCartesianProduct({s32}, {s64, s32})
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.minScalar(0, s32);
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// Int to FP conversion instructions
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getActionDefinitionsBuilder(G_SITOFP)
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.legalForCartesianProduct({s64, s32}, {s32})
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.libcallForCartesianProduct({s64, s32}, {s64})
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.minScalar(1, s32);
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getActionDefinitionsBuilder(G_UITOFP)
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.libcallForCartesianProduct({s64, s32}, {s64})
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.customForCartesianProduct({s64, s32}, {s32})
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.minScalar(1, s32);
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getActionDefinitionsBuilder(G_SEXT_INREG).lower();
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getActionDefinitionsBuilder({G_MEMCPY, G_MEMMOVE, G_MEMSET}).libcall();
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computeTables();
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verify(*ST.getInstrInfo());
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}
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bool MipsLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
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MachineInstr &MI) const {
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using namespace TargetOpcode;
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MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
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MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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switch (MI.getOpcode()) {
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case G_LOAD:
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case G_STORE: {
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unsigned MemSize = (**MI.memoperands_begin()).getSize();
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Register Val = MI.getOperand(0).getReg();
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unsigned Size = MRI.getType(Val).getSizeInBits();
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MachineMemOperand *MMOBase = *MI.memoperands_begin();
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assert(MemSize <= 8 && "MemSize is too large");
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assert(Size <= 64 && "Scalar size is too large");
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|
// Split MemSize into two, P2HalfMemSize is largest power of two smaller
|
||
|
|
// then MemSize. e.g. 8 = 4 + 4 , 6 = 4 + 2, 3 = 2 + 1.
|
||
|
|
unsigned P2HalfMemSize, RemMemSize;
|
||
|
|
if (isPowerOf2_64(MemSize)) {
|
||
|
|
P2HalfMemSize = RemMemSize = MemSize / 2;
|
||
|
|
} else {
|
||
|
|
P2HalfMemSize = 1 << Log2_32(MemSize);
|
||
|
|
RemMemSize = MemSize - P2HalfMemSize;
|
||
|
|
}
|
||
|
|
|
||
|
|
Register BaseAddr = MI.getOperand(1).getReg();
|
||
|
|
LLT PtrTy = MRI.getType(BaseAddr);
|
||
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
||
|
|
|
||
|
|
auto P2HalfMemOp = MF.getMachineMemOperand(MMOBase, 0, P2HalfMemSize);
|
||
|
|
auto RemMemOp = MF.getMachineMemOperand(MMOBase, P2HalfMemSize, RemMemSize);
|
||
|
|
|
||
|
|
if (MI.getOpcode() == G_STORE) {
|
||
|
|
// Widen Val to s32 or s64 in order to create legal G_LSHR or G_UNMERGE.
|
||
|
|
if (Size < 32)
|
||
|
|
Val = MIRBuilder.buildAnyExt(s32, Val).getReg(0);
|
||
|
|
if (Size > 32 && Size < 64)
|
||
|
|
Val = MIRBuilder.buildAnyExt(s64, Val).getReg(0);
|
||
|
|
|
||
|
|
auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize);
|
||
|
|
auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize);
|
||
|
|
|
||
|
|
if (MI.getOpcode() == G_STORE && MemSize <= 4) {
|
||
|
|
MIRBuilder.buildStore(Val, BaseAddr, *P2HalfMemOp);
|
||
|
|
auto C_P2Half_InBits = MIRBuilder.buildConstant(s32, P2HalfMemSize * 8);
|
||
|
|
auto Shift = MIRBuilder.buildLShr(s32, Val, C_P2Half_InBits);
|
||
|
|
MIRBuilder.buildStore(Shift, Addr, *RemMemOp);
|
||
|
|
} else {
|
||
|
|
auto Unmerge = MIRBuilder.buildUnmerge(s32, Val);
|
||
|
|
MIRBuilder.buildStore(Unmerge.getReg(0), BaseAddr, *P2HalfMemOp);
|
||
|
|
MIRBuilder.buildStore(Unmerge.getReg(1), Addr, *RemMemOp);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (MI.getOpcode() == G_LOAD) {
|
||
|
|
|
||
|
|
if (MemSize <= 4) {
|
||
|
|
// This is anyextending load, use 4 byte lwr/lwl.
|
||
|
|
auto *Load4MMO = MF.getMachineMemOperand(MMOBase, 0, 4);
|
||
|
|
|
||
|
|
if (Size == 32)
|
||
|
|
MIRBuilder.buildLoad(Val, BaseAddr, *Load4MMO);
|
||
|
|
else {
|
||
|
|
auto Load = MIRBuilder.buildLoad(s32, BaseAddr, *Load4MMO);
|
||
|
|
MIRBuilder.buildTrunc(Val, Load.getReg(0));
|
||
|
|
}
|
||
|
|
|
||
|
|
} else {
|
||
|
|
auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize);
|
||
|
|
auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize);
|
||
|
|
|
||
|
|
auto Load_P2Half = MIRBuilder.buildLoad(s32, BaseAddr, *P2HalfMemOp);
|
||
|
|
auto Load_Rem = MIRBuilder.buildLoad(s32, Addr, *RemMemOp);
|
||
|
|
|
||
|
|
if (Size == 64)
|
||
|
|
MIRBuilder.buildMerge(Val, {Load_P2Half, Load_Rem});
|
||
|
|
else {
|
||
|
|
auto Merge = MIRBuilder.buildMerge(s64, {Load_P2Half, Load_Rem});
|
||
|
|
MIRBuilder.buildTrunc(Val, Merge);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
MI.eraseFromParent();
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
case G_UITOFP: {
|
||
|
|
Register Dst = MI.getOperand(0).getReg();
|
||
|
|
Register Src = MI.getOperand(1).getReg();
|
||
|
|
LLT DstTy = MRI.getType(Dst);
|
||
|
|
LLT SrcTy = MRI.getType(Src);
|
||
|
|
|
||
|
|
if (SrcTy != s32)
|
||
|
|
return false;
|
||
|
|
if (DstTy != s32 && DstTy != s64)
|
||
|
|
return false;
|
||
|
|
|
||
|
|
// Let 0xABCDEFGH be given unsigned in MI.getOperand(1). First let's convert
|
||
|
|
// unsigned to double. Mantissa has 52 bits so we use following trick:
|
||
|
|
// First make floating point bit mask 0x43300000ABCDEFGH.
|
||
|
|
// Mask represents 2^52 * 0x1.00000ABCDEFGH i.e. 0x100000ABCDEFGH.0 .
|
||
|
|
// Next, subtract 2^52 * 0x1.0000000000000 i.e. 0x10000000000000.0 from it.
|
||
|
|
// Done. Trunc double to float if needed.
|
||
|
|
|
||
|
|
auto C_HiMask = MIRBuilder.buildConstant(s32, UINT32_C(0x43300000));
|
||
|
|
auto Bitcast = MIRBuilder.buildMerge(s64, {Src, C_HiMask.getReg(0)});
|
||
|
|
|
||
|
|
MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant(
|
||
|
|
s64, BitsToDouble(UINT64_C(0x4330000000000000)));
|
||
|
|
|
||
|
|
if (DstTy == s64)
|
||
|
|
MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP);
|
||
|
|
else {
|
||
|
|
MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP);
|
||
|
|
MIRBuilder.buildFPTrunc(Dst, ResF64);
|
||
|
|
}
|
||
|
|
|
||
|
|
MI.eraseFromParent();
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
default:
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode,
|
||
|
|
MachineIRBuilder &MIRBuilder,
|
||
|
|
const MipsSubtarget &ST) {
|
||
|
|
assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
|
||
|
|
if (!MIRBuilder.buildInstr(Opcode)
|
||
|
|
.add(MI.getOperand(0))
|
||
|
|
.add(MI.getOperand(2))
|
||
|
|
.add(MI.getOperand(3))
|
||
|
|
.constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(),
|
||
|
|
*ST.getRegBankInfo()))
|
||
|
|
return false;
|
||
|
|
MI.eraseFromParent();
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
|
||
|
|
MachineIRBuilder &MIRBuilder,
|
||
|
|
const MipsSubtarget &ST) {
|
||
|
|
assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
|
||
|
|
MIRBuilder.buildInstr(Opcode)
|
||
|
|
.add(MI.getOperand(0))
|
||
|
|
.add(MI.getOperand(2))
|
||
|
|
.add(MI.getOperand(3));
|
||
|
|
MI.eraseFromParent();
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
|
||
|
|
MachineIRBuilder &MIRBuilder,
|
||
|
|
const MipsSubtarget &ST) {
|
||
|
|
assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
|
||
|
|
MIRBuilder.buildInstr(Opcode)
|
||
|
|
.add(MI.getOperand(0))
|
||
|
|
.add(MI.getOperand(2));
|
||
|
|
MI.eraseFromParent();
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool MipsLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
|
||
|
|
MachineInstr &MI) const {
|
||
|
|
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
|
||
|
|
const MipsSubtarget &ST =
|
||
|
|
static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget());
|
||
|
|
const MipsInstrInfo &TII = *ST.getInstrInfo();
|
||
|
|
const MipsRegisterInfo &TRI = *ST.getRegisterInfo();
|
||
|
|
const RegisterBankInfo &RBI = *ST.getRegBankInfo();
|
||
|
|
|
||
|
|
switch (MI.getIntrinsicID()) {
|
||
|
|
case Intrinsic::trap: {
|
||
|
|
MachineInstr *Trap = MIRBuilder.buildInstr(Mips::TRAP);
|
||
|
|
MI.eraseFromParent();
|
||
|
|
return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI);
|
||
|
|
}
|
||
|
|
case Intrinsic::vacopy: {
|
||
|
|
MachinePointerInfo MPO;
|
||
|
|
auto Tmp =
|
||
|
|
MIRBuilder.buildLoad(LLT::pointer(0, 32), MI.getOperand(2),
|
||
|
|
*MI.getMF()->getMachineMemOperand(
|
||
|
|
MPO, MachineMemOperand::MOLoad, 4, Align(4)));
|
||
|
|
MIRBuilder.buildStore(Tmp, MI.getOperand(1),
|
||
|
|
*MI.getMF()->getMachineMemOperand(
|
||
|
|
MPO, MachineMemOperand::MOStore, 4, Align(4)));
|
||
|
|
MI.eraseFromParent();
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
case Intrinsic::mips_addv_b:
|
||
|
|
case Intrinsic::mips_addv_h:
|
||
|
|
case Intrinsic::mips_addv_w:
|
||
|
|
case Intrinsic::mips_addv_d:
|
||
|
|
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_ADD, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_addvi_b:
|
||
|
|
return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_addvi_h:
|
||
|
|
return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_addvi_w:
|
||
|
|
return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_addvi_d:
|
||
|
|
return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_subv_b:
|
||
|
|
case Intrinsic::mips_subv_h:
|
||
|
|
case Intrinsic::mips_subv_w:
|
||
|
|
case Intrinsic::mips_subv_d:
|
||
|
|
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SUB, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_subvi_b:
|
||
|
|
return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_B, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_subvi_h:
|
||
|
|
return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_H, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_subvi_w:
|
||
|
|
return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_subvi_d:
|
||
|
|
return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_mulv_b:
|
||
|
|
case Intrinsic::mips_mulv_h:
|
||
|
|
case Intrinsic::mips_mulv_w:
|
||
|
|
case Intrinsic::mips_mulv_d:
|
||
|
|
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_div_s_b:
|
||
|
|
case Intrinsic::mips_div_s_h:
|
||
|
|
case Intrinsic::mips_div_s_w:
|
||
|
|
case Intrinsic::mips_div_s_d:
|
||
|
|
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SDIV, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_mod_s_b:
|
||
|
|
case Intrinsic::mips_mod_s_h:
|
||
|
|
case Intrinsic::mips_mod_s_w:
|
||
|
|
case Intrinsic::mips_mod_s_d:
|
||
|
|
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SREM, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_div_u_b:
|
||
|
|
case Intrinsic::mips_div_u_h:
|
||
|
|
case Intrinsic::mips_div_u_w:
|
||
|
|
case Intrinsic::mips_div_u_d:
|
||
|
|
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UDIV, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_mod_u_b:
|
||
|
|
case Intrinsic::mips_mod_u_h:
|
||
|
|
case Intrinsic::mips_mod_u_w:
|
||
|
|
case Intrinsic::mips_mod_u_d:
|
||
|
|
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UREM, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_fadd_w:
|
||
|
|
case Intrinsic::mips_fadd_d:
|
||
|
|
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FADD, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_fsub_w:
|
||
|
|
case Intrinsic::mips_fsub_d:
|
||
|
|
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FSUB, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_fmul_w:
|
||
|
|
case Intrinsic::mips_fmul_d:
|
||
|
|
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FMUL, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_fdiv_w:
|
||
|
|
case Intrinsic::mips_fdiv_d:
|
||
|
|
return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FDIV, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_fmax_a_w:
|
||
|
|
return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_W, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_fmax_a_d:
|
||
|
|
return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_D, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_fsqrt_w:
|
||
|
|
return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST);
|
||
|
|
case Intrinsic::mips_fsqrt_d:
|
||
|
|
return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST);
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
return true;
|
||
|
|
}
|