822 lines
27 KiB
C++
822 lines
27 KiB
C++
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//===-- LanaiInstrInfo.cpp - Lanai Instruction Information ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Lanai implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "LanaiInstrInfo.h"
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#include "LanaiAluCode.h"
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#include "LanaiCondCode.h"
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#include "MCTargetDesc/LanaiBaseInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "LanaiGenInstrInfo.inc"
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LanaiInstrInfo::LanaiInstrInfo()
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: LanaiGenInstrInfo(Lanai::ADJCALLSTACKDOWN, Lanai::ADJCALLSTACKUP),
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RegisterInfo() {}
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void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator Position,
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const DebugLoc &DL,
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MCRegister DestinationRegister,
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MCRegister SourceRegister,
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bool KillSource) const {
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if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
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llvm_unreachable("Impossible reg-to-reg copy");
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}
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BuildMI(MBB, Position, DL, get(Lanai::OR_I_LO), DestinationRegister)
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.addReg(SourceRegister, getKillRegState(KillSource))
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.addImm(0);
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}
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void LanaiInstrInfo::storeRegToStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
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Register SourceRegister, bool IsKill, int FrameIndex,
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const TargetRegisterClass *RegisterClass,
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const TargetRegisterInfo * /*RegisterInfo*/) const {
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DebugLoc DL;
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if (Position != MBB.end()) {
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DL = Position->getDebugLoc();
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}
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if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
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llvm_unreachable("Can't store this register to stack slot");
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}
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BuildMI(MBB, Position, DL, get(Lanai::SW_RI))
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.addReg(SourceRegister, getKillRegState(IsKill))
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.addFrameIndex(FrameIndex)
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.addImm(0)
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.addImm(LPAC::ADD);
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}
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void LanaiInstrInfo::loadRegFromStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
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Register DestinationRegister, int FrameIndex,
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const TargetRegisterClass *RegisterClass,
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const TargetRegisterInfo * /*RegisterInfo*/) const {
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DebugLoc DL;
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if (Position != MBB.end()) {
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DL = Position->getDebugLoc();
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}
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if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
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llvm_unreachable("Can't load this register from stack slot");
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}
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BuildMI(MBB, Position, DL, get(Lanai::LDW_RI), DestinationRegister)
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.addFrameIndex(FrameIndex)
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.addImm(0)
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.addImm(LPAC::ADD);
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}
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bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(
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const MachineInstr &MIa, const MachineInstr &MIb) const {
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assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
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assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
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if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
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MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
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return false;
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// Retrieve the base register, offset from the base register and width. Width
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// is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
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// base registers are identical, and the offset of a lower memory access +
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// the width doesn't overlap the offset of a higher memory access,
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// then the memory accesses are different.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
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int64_t OffsetA = 0, OffsetB = 0;
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unsigned int WidthA = 0, WidthB = 0;
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if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
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getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
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if (BaseOpA->isIdenticalTo(*BaseOpB)) {
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int LowOffset = std::min(OffsetA, OffsetB);
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int HighOffset = std::max(OffsetA, OffsetB);
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int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
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if (LowOffset + LowWidth <= HighOffset)
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return true;
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}
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}
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return false;
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}
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bool LanaiInstrInfo::expandPostRAPseudo(MachineInstr & /*MI*/) const {
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return false;
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}
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static LPCC::CondCode getOppositeCondition(LPCC::CondCode CC) {
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switch (CC) {
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case LPCC::ICC_T: // true
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return LPCC::ICC_F;
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case LPCC::ICC_F: // false
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return LPCC::ICC_T;
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case LPCC::ICC_HI: // high
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return LPCC::ICC_LS;
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case LPCC::ICC_LS: // low or same
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return LPCC::ICC_HI;
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case LPCC::ICC_CC: // carry cleared
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return LPCC::ICC_CS;
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case LPCC::ICC_CS: // carry set
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return LPCC::ICC_CC;
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case LPCC::ICC_NE: // not equal
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return LPCC::ICC_EQ;
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case LPCC::ICC_EQ: // equal
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return LPCC::ICC_NE;
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case LPCC::ICC_VC: // oVerflow cleared
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return LPCC::ICC_VS;
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case LPCC::ICC_VS: // oVerflow set
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return LPCC::ICC_VC;
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case LPCC::ICC_PL: // plus (note: 0 is "minus" too here)
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return LPCC::ICC_MI;
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case LPCC::ICC_MI: // minus
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return LPCC::ICC_PL;
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case LPCC::ICC_GE: // greater than or equal
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return LPCC::ICC_LT;
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case LPCC::ICC_LT: // less than
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return LPCC::ICC_GE;
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case LPCC::ICC_GT: // greater than
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return LPCC::ICC_LE;
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case LPCC::ICC_LE: // less than or equal
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return LPCC::ICC_GT;
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default:
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llvm_unreachable("Invalid condtional code");
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}
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}
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std::pair<unsigned, unsigned>
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LanaiInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
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return std::make_pair(TF, 0u);
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}
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ArrayRef<std::pair<unsigned, const char *>>
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LanaiInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
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using namespace LanaiII;
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static const std::pair<unsigned, const char *> TargetFlags[] = {
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{MO_ABS_HI, "lanai-hi"},
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{MO_ABS_LO, "lanai-lo"},
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{MO_NO_FLAG, "lanai-nf"}};
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return makeArrayRef(TargetFlags);
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}
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bool LanaiInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
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Register &SrcReg2, int &CmpMask,
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int &CmpValue) const {
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switch (MI.getOpcode()) {
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default:
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break;
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case Lanai::SFSUB_F_RI_LO:
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case Lanai::SFSUB_F_RI_HI:
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SrcReg = MI.getOperand(0).getReg();
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SrcReg2 = Register();
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CmpMask = ~0;
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CmpValue = MI.getOperand(1).getImm();
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return true;
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case Lanai::SFSUB_F_RR:
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SrcReg = MI.getOperand(0).getReg();
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SrcReg2 = MI.getOperand(1).getReg();
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CmpMask = ~0;
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CmpValue = 0;
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return true;
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}
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return false;
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}
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// isRedundantFlagInstr - check whether the first instruction, whose only
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// purpose is to update flags, can be made redundant.
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// * SFSUB_F_RR can be made redundant by SUB_RI if the operands are the same.
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// * SFSUB_F_RI can be made redundant by SUB_I if the operands are the same.
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inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
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unsigned SrcReg2, int ImmValue,
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MachineInstr *OI) {
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if (CmpI->getOpcode() == Lanai::SFSUB_F_RR &&
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OI->getOpcode() == Lanai::SUB_R &&
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((OI->getOperand(1).getReg() == SrcReg &&
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OI->getOperand(2).getReg() == SrcReg2) ||
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(OI->getOperand(1).getReg() == SrcReg2 &&
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OI->getOperand(2).getReg() == SrcReg)))
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return true;
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if (((CmpI->getOpcode() == Lanai::SFSUB_F_RI_LO &&
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OI->getOpcode() == Lanai::SUB_I_LO) ||
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(CmpI->getOpcode() == Lanai::SFSUB_F_RI_HI &&
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OI->getOpcode() == Lanai::SUB_I_HI)) &&
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OI->getOperand(1).getReg() == SrcReg &&
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OI->getOperand(2).getImm() == ImmValue)
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return true;
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return false;
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}
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inline static unsigned flagSettingOpcodeVariant(unsigned OldOpcode) {
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switch (OldOpcode) {
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case Lanai::ADD_I_HI:
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return Lanai::ADD_F_I_HI;
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case Lanai::ADD_I_LO:
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return Lanai::ADD_F_I_LO;
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case Lanai::ADD_R:
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return Lanai::ADD_F_R;
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case Lanai::ADDC_I_HI:
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return Lanai::ADDC_F_I_HI;
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case Lanai::ADDC_I_LO:
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return Lanai::ADDC_F_I_LO;
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case Lanai::ADDC_R:
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return Lanai::ADDC_F_R;
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case Lanai::AND_I_HI:
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return Lanai::AND_F_I_HI;
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case Lanai::AND_I_LO:
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return Lanai::AND_F_I_LO;
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case Lanai::AND_R:
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return Lanai::AND_F_R;
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case Lanai::OR_I_HI:
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return Lanai::OR_F_I_HI;
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case Lanai::OR_I_LO:
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return Lanai::OR_F_I_LO;
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case Lanai::OR_R:
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return Lanai::OR_F_R;
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case Lanai::SL_I:
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return Lanai::SL_F_I;
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case Lanai::SRL_R:
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return Lanai::SRL_F_R;
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case Lanai::SA_I:
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return Lanai::SA_F_I;
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case Lanai::SRA_R:
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return Lanai::SRA_F_R;
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case Lanai::SUB_I_HI:
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return Lanai::SUB_F_I_HI;
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case Lanai::SUB_I_LO:
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return Lanai::SUB_F_I_LO;
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case Lanai::SUB_R:
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return Lanai::SUB_F_R;
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case Lanai::SUBB_I_HI:
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return Lanai::SUBB_F_I_HI;
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case Lanai::SUBB_I_LO:
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return Lanai::SUBB_F_I_LO;
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case Lanai::SUBB_R:
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return Lanai::SUBB_F_R;
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case Lanai::XOR_I_HI:
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return Lanai::XOR_F_I_HI;
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case Lanai::XOR_I_LO:
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return Lanai::XOR_F_I_LO;
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case Lanai::XOR_R:
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return Lanai::XOR_F_R;
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default:
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return Lanai::NOP;
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}
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}
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bool LanaiInstrInfo::optimizeCompareInstr(
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MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int /*CmpMask*/,
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int CmpValue, const MachineRegisterInfo *MRI) const {
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// Get the unique definition of SrcReg.
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MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
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if (!MI)
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return false;
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// Get ready to iterate backward from CmpInstr.
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MachineBasicBlock::iterator I = CmpInstr, E = MI,
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B = CmpInstr.getParent()->begin();
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// Early exit if CmpInstr is at the beginning of the BB.
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if (I == B)
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return false;
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// There are two possible candidates which can be changed to set SR:
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// One is MI, the other is a SUB instruction.
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// * For SFSUB_F_RR(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
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// * For SFSUB_F_RI(r1, CmpValue), we are looking for SUB(r1, CmpValue).
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MachineInstr *Sub = nullptr;
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if (SrcReg2 != 0)
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// MI is not a candidate to transform into a flag setting instruction.
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MI = nullptr;
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else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
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// Conservatively refuse to convert an instruction which isn't in the same
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// BB as the comparison. Don't return if SFSUB_F_RI and CmpValue != 0 as Sub
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// may still be a candidate.
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if (CmpInstr.getOpcode() == Lanai::SFSUB_F_RI_LO)
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MI = nullptr;
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else
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return false;
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}
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// Check that SR isn't set between the comparison instruction and the
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// instruction we want to change while searching for Sub.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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for (--I; I != E; --I) {
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const MachineInstr &Instr = *I;
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if (Instr.modifiesRegister(Lanai::SR, TRI) ||
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Instr.readsRegister(Lanai::SR, TRI))
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// This instruction modifies or uses SR after the one we want to change.
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// We can't do this transformation.
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return false;
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// Check whether CmpInstr can be made redundant by the current instruction.
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if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
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Sub = &*I;
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break;
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}
|
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// Don't search outside the containing basic block.
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||
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if (I == B)
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return false;
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}
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// Return false if no candidates exist.
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||
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if (!MI && !Sub)
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return false;
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// The single candidate is called MI.
|
||
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|
if (!MI)
|
||
|
|
MI = Sub;
|
||
|
|
|
||
|
|
if (flagSettingOpcodeVariant(MI->getOpcode()) != Lanai::NOP) {
|
||
|
|
bool isSafe = false;
|
||
|
|
|
||
|
|
SmallVector<std::pair<MachineOperand *, LPCC::CondCode>, 4>
|
||
|
|
OperandsToUpdate;
|
||
|
|
I = CmpInstr;
|
||
|
|
E = CmpInstr.getParent()->end();
|
||
|
|
while (!isSafe && ++I != E) {
|
||
|
|
const MachineInstr &Instr = *I;
|
||
|
|
for (unsigned IO = 0, EO = Instr.getNumOperands(); !isSafe && IO != EO;
|
||
|
|
++IO) {
|
||
|
|
const MachineOperand &MO = Instr.getOperand(IO);
|
||
|
|
if (MO.isRegMask() && MO.clobbersPhysReg(Lanai::SR)) {
|
||
|
|
isSafe = true;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
if (!MO.isReg() || MO.getReg() != Lanai::SR)
|
||
|
|
continue;
|
||
|
|
if (MO.isDef()) {
|
||
|
|
isSafe = true;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
// Condition code is after the operand before SR.
|
||
|
|
LPCC::CondCode CC;
|
||
|
|
CC = (LPCC::CondCode)Instr.getOperand(IO - 1).getImm();
|
||
|
|
|
||
|
|
if (Sub) {
|
||
|
|
LPCC::CondCode NewCC = getOppositeCondition(CC);
|
||
|
|
if (NewCC == LPCC::ICC_T)
|
||
|
|
return false;
|
||
|
|
// If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on
|
||
|
|
// CMP needs to be updated to be based on SUB. Push the condition
|
||
|
|
// code operands to OperandsToUpdate. If it is safe to remove
|
||
|
|
// CmpInstr, the condition code of these operands will be modified.
|
||
|
|
if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
|
||
|
|
Sub->getOperand(2).getReg() == SrcReg) {
|
||
|
|
OperandsToUpdate.push_back(
|
||
|
|
std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
// No Sub, so this is x = <op> y, z; cmp x, 0.
|
||
|
|
switch (CC) {
|
||
|
|
case LPCC::ICC_EQ: // Z
|
||
|
|
case LPCC::ICC_NE: // Z
|
||
|
|
case LPCC::ICC_MI: // N
|
||
|
|
case LPCC::ICC_PL: // N
|
||
|
|
case LPCC::ICC_F: // none
|
||
|
|
case LPCC::ICC_T: // none
|
||
|
|
// SR can be used multiple times, we should continue.
|
||
|
|
break;
|
||
|
|
case LPCC::ICC_CS: // C
|
||
|
|
case LPCC::ICC_CC: // C
|
||
|
|
case LPCC::ICC_VS: // V
|
||
|
|
case LPCC::ICC_VC: // V
|
||
|
|
case LPCC::ICC_HI: // C Z
|
||
|
|
case LPCC::ICC_LS: // C Z
|
||
|
|
case LPCC::ICC_GE: // N V
|
||
|
|
case LPCC::ICC_LT: // N V
|
||
|
|
case LPCC::ICC_GT: // Z N V
|
||
|
|
case LPCC::ICC_LE: // Z N V
|
||
|
|
// The instruction uses the V bit or C bit which is not safe.
|
||
|
|
return false;
|
||
|
|
case LPCC::UNKNOWN:
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// If SR is not killed nor re-defined, we should check whether it is
|
||
|
|
// live-out. If it is live-out, do not optimize.
|
||
|
|
if (!isSafe) {
|
||
|
|
MachineBasicBlock *MBB = CmpInstr.getParent();
|
||
|
|
for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
|
||
|
|
SE = MBB->succ_end();
|
||
|
|
SI != SE; ++SI)
|
||
|
|
if ((*SI)->isLiveIn(Lanai::SR))
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Toggle the optional operand to SR.
|
||
|
|
MI->setDesc(get(flagSettingOpcodeVariant(MI->getOpcode())));
|
||
|
|
MI->addRegisterDefined(Lanai::SR);
|
||
|
|
CmpInstr.eraseFromParent();
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool LanaiInstrInfo::analyzeSelect(const MachineInstr &MI,
|
||
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
||
|
|
unsigned &TrueOp, unsigned &FalseOp,
|
||
|
|
bool &Optimizable) const {
|
||
|
|
assert(MI.getOpcode() == Lanai::SELECT && "unknown select instruction");
|
||
|
|
// Select operands:
|
||
|
|
// 0: Def.
|
||
|
|
// 1: True use.
|
||
|
|
// 2: False use.
|
||
|
|
// 3: Condition code.
|
||
|
|
TrueOp = 1;
|
||
|
|
FalseOp = 2;
|
||
|
|
Cond.push_back(MI.getOperand(3));
|
||
|
|
Optimizable = true;
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Identify instructions that can be folded into a SELECT instruction, and
|
||
|
|
// return the defining instruction.
|
||
|
|
static MachineInstr *canFoldIntoSelect(Register Reg,
|
||
|
|
const MachineRegisterInfo &MRI) {
|
||
|
|
if (!Reg.isVirtual())
|
||
|
|
return nullptr;
|
||
|
|
if (!MRI.hasOneNonDBGUse(Reg))
|
||
|
|
return nullptr;
|
||
|
|
MachineInstr *MI = MRI.getVRegDef(Reg);
|
||
|
|
if (!MI)
|
||
|
|
return nullptr;
|
||
|
|
// MI is folded into the SELECT by predicating it.
|
||
|
|
if (!MI->isPredicable())
|
||
|
|
return nullptr;
|
||
|
|
// Check if MI has any non-dead defs or physreg uses. This also detects
|
||
|
|
// predicated instructions which will be reading SR.
|
||
|
|
for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
|
||
|
|
const MachineOperand &MO = MI->getOperand(i);
|
||
|
|
// Reject frame index operands.
|
||
|
|
if (MO.isFI() || MO.isCPI() || MO.isJTI())
|
||
|
|
return nullptr;
|
||
|
|
if (!MO.isReg())
|
||
|
|
continue;
|
||
|
|
// MI can't have any tied operands, that would conflict with predication.
|
||
|
|
if (MO.isTied())
|
||
|
|
return nullptr;
|
||
|
|
if (Register::isPhysicalRegister(MO.getReg()))
|
||
|
|
return nullptr;
|
||
|
|
if (MO.isDef() && !MO.isDead())
|
||
|
|
return nullptr;
|
||
|
|
}
|
||
|
|
bool DontMoveAcrossStores = true;
|
||
|
|
if (!MI->isSafeToMove(/*AliasAnalysis=*/nullptr, DontMoveAcrossStores))
|
||
|
|
return nullptr;
|
||
|
|
return MI;
|
||
|
|
}
|
||
|
|
|
||
|
|
MachineInstr *
|
||
|
|
LanaiInstrInfo::optimizeSelect(MachineInstr &MI,
|
||
|
|
SmallPtrSetImpl<MachineInstr *> &SeenMIs,
|
||
|
|
bool /*PreferFalse*/) const {
|
||
|
|
assert(MI.getOpcode() == Lanai::SELECT && "unknown select instruction");
|
||
|
|
MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
|
||
|
|
MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI);
|
||
|
|
bool Invert = !DefMI;
|
||
|
|
if (!DefMI)
|
||
|
|
DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI);
|
||
|
|
if (!DefMI)
|
||
|
|
return nullptr;
|
||
|
|
|
||
|
|
// Find new register class to use.
|
||
|
|
MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2);
|
||
|
|
Register DestReg = MI.getOperand(0).getReg();
|
||
|
|
const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
|
||
|
|
if (!MRI.constrainRegClass(DestReg, PreviousClass))
|
||
|
|
return nullptr;
|
||
|
|
|
||
|
|
// Create a new predicated version of DefMI.
|
||
|
|
MachineInstrBuilder NewMI =
|
||
|
|
BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
|
||
|
|
|
||
|
|
// Copy all the DefMI operands, excluding its (null) predicate.
|
||
|
|
const MCInstrDesc &DefDesc = DefMI->getDesc();
|
||
|
|
for (unsigned i = 1, e = DefDesc.getNumOperands();
|
||
|
|
i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
|
||
|
|
NewMI.add(DefMI->getOperand(i));
|
||
|
|
|
||
|
|
unsigned CondCode = MI.getOperand(3).getImm();
|
||
|
|
if (Invert)
|
||
|
|
NewMI.addImm(getOppositeCondition(LPCC::CondCode(CondCode)));
|
||
|
|
else
|
||
|
|
NewMI.addImm(CondCode);
|
||
|
|
NewMI.copyImplicitOps(MI);
|
||
|
|
|
||
|
|
// The output register value when the predicate is false is an implicit
|
||
|
|
// register operand tied to the first def. The tie makes the register
|
||
|
|
// allocator ensure the FalseReg is allocated the same register as operand 0.
|
||
|
|
FalseReg.setImplicit();
|
||
|
|
NewMI.add(FalseReg);
|
||
|
|
NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
|
||
|
|
|
||
|
|
// Update SeenMIs set: register newly created MI and erase removed DefMI.
|
||
|
|
SeenMIs.insert(NewMI);
|
||
|
|
SeenMIs.erase(DefMI);
|
||
|
|
|
||
|
|
// If MI is inside a loop, and DefMI is outside the loop, then kill flags on
|
||
|
|
// DefMI would be invalid when transferred inside the loop. Checking for a
|
||
|
|
// loop is expensive, but at least remove kill flags if they are in different
|
||
|
|
// BBs.
|
||
|
|
if (DefMI->getParent() != MI.getParent())
|
||
|
|
NewMI->clearKillInfo();
|
||
|
|
|
||
|
|
// The caller will erase MI, but not DefMI.
|
||
|
|
DefMI->eraseFromParent();
|
||
|
|
return NewMI;
|
||
|
|
}
|
||
|
|
|
||
|
|
// The analyzeBranch function is used to examine conditional instructions and
|
||
|
|
// remove unnecessary instructions. This method is used by BranchFolder and
|
||
|
|
// IfConverter machine function passes to improve the CFG.
|
||
|
|
// - TrueBlock is set to the destination if condition evaluates true (it is the
|
||
|
|
// nullptr if the destination is the fall-through branch);
|
||
|
|
// - FalseBlock is set to the destination if condition evaluates to false (it
|
||
|
|
// is the nullptr if the branch is unconditional);
|
||
|
|
// - condition is populated with machine operands needed to generate the branch
|
||
|
|
// to insert in insertBranch;
|
||
|
|
// Returns: false if branch could successfully be analyzed.
|
||
|
|
bool LanaiInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
|
||
|
|
MachineBasicBlock *&TrueBlock,
|
||
|
|
MachineBasicBlock *&FalseBlock,
|
||
|
|
SmallVectorImpl<MachineOperand> &Condition,
|
||
|
|
bool AllowModify) const {
|
||
|
|
// Iterator to current instruction being considered.
|
||
|
|
MachineBasicBlock::iterator Instruction = MBB.end();
|
||
|
|
|
||
|
|
// Start from the bottom of the block and work up, examining the
|
||
|
|
// terminator instructions.
|
||
|
|
while (Instruction != MBB.begin()) {
|
||
|
|
--Instruction;
|
||
|
|
|
||
|
|
// Skip over debug instructions.
|
||
|
|
if (Instruction->isDebugInstr())
|
||
|
|
continue;
|
||
|
|
|
||
|
|
// Working from the bottom, when we see a non-terminator
|
||
|
|
// instruction, we're done.
|
||
|
|
if (!isUnpredicatedTerminator(*Instruction))
|
||
|
|
break;
|
||
|
|
|
||
|
|
// A terminator that isn't a branch can't easily be handled
|
||
|
|
// by this analysis.
|
||
|
|
if (!Instruction->isBranch())
|
||
|
|
return true;
|
||
|
|
|
||
|
|
// Handle unconditional branches.
|
||
|
|
if (Instruction->getOpcode() == Lanai::BT) {
|
||
|
|
if (!AllowModify) {
|
||
|
|
TrueBlock = Instruction->getOperand(0).getMBB();
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// If the block has any instructions after a branch, delete them.
|
||
|
|
while (std::next(Instruction) != MBB.end()) {
|
||
|
|
std::next(Instruction)->eraseFromParent();
|
||
|
|
}
|
||
|
|
|
||
|
|
Condition.clear();
|
||
|
|
FalseBlock = nullptr;
|
||
|
|
|
||
|
|
// Delete the jump if it's equivalent to a fall-through.
|
||
|
|
if (MBB.isLayoutSuccessor(Instruction->getOperand(0).getMBB())) {
|
||
|
|
TrueBlock = nullptr;
|
||
|
|
Instruction->eraseFromParent();
|
||
|
|
Instruction = MBB.end();
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// TrueBlock is used to indicate the unconditional destination.
|
||
|
|
TrueBlock = Instruction->getOperand(0).getMBB();
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Handle conditional branches
|
||
|
|
unsigned Opcode = Instruction->getOpcode();
|
||
|
|
if (Opcode != Lanai::BRCC)
|
||
|
|
return true; // Unknown opcode.
|
||
|
|
|
||
|
|
// Multiple conditional branches are not handled here so only proceed if
|
||
|
|
// there are no conditions enqueued.
|
||
|
|
if (Condition.empty()) {
|
||
|
|
LPCC::CondCode BranchCond =
|
||
|
|
static_cast<LPCC::CondCode>(Instruction->getOperand(1).getImm());
|
||
|
|
|
||
|
|
// TrueBlock is the target of the previously seen unconditional branch.
|
||
|
|
FalseBlock = TrueBlock;
|
||
|
|
TrueBlock = Instruction->getOperand(0).getMBB();
|
||
|
|
Condition.push_back(MachineOperand::CreateImm(BranchCond));
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Multiple conditional branches are not handled.
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Return false indicating branch successfully analyzed.
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
// reverseBranchCondition - Reverses the branch condition of the specified
|
||
|
|
// condition list, returning false on success and true if it cannot be
|
||
|
|
// reversed.
|
||
|
|
bool LanaiInstrInfo::reverseBranchCondition(
|
||
|
|
SmallVectorImpl<llvm::MachineOperand> &Condition) const {
|
||
|
|
assert((Condition.size() == 1) &&
|
||
|
|
"Lanai branch conditions should have one component.");
|
||
|
|
|
||
|
|
LPCC::CondCode BranchCond =
|
||
|
|
static_cast<LPCC::CondCode>(Condition[0].getImm());
|
||
|
|
Condition[0].setImm(getOppositeCondition(BranchCond));
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Insert the branch with condition specified in condition and given targets
|
||
|
|
// (TrueBlock and FalseBlock). This function returns the number of machine
|
||
|
|
// instructions inserted.
|
||
|
|
unsigned LanaiInstrInfo::insertBranch(MachineBasicBlock &MBB,
|
||
|
|
MachineBasicBlock *TrueBlock,
|
||
|
|
MachineBasicBlock *FalseBlock,
|
||
|
|
ArrayRef<MachineOperand> Condition,
|
||
|
|
const DebugLoc &DL,
|
||
|
|
int *BytesAdded) const {
|
||
|
|
// Shouldn't be a fall through.
|
||
|
|
assert(TrueBlock && "insertBranch must not be told to insert a fallthrough");
|
||
|
|
assert(!BytesAdded && "code size not handled");
|
||
|
|
|
||
|
|
// If condition is empty then an unconditional branch is being inserted.
|
||
|
|
if (Condition.empty()) {
|
||
|
|
assert(!FalseBlock && "Unconditional branch with multiple successors!");
|
||
|
|
BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(TrueBlock);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Else a conditional branch is inserted.
|
||
|
|
assert((Condition.size() == 1) &&
|
||
|
|
"Lanai branch conditions should have one component.");
|
||
|
|
unsigned ConditionalCode = Condition[0].getImm();
|
||
|
|
BuildMI(&MBB, DL, get(Lanai::BRCC)).addMBB(TrueBlock).addImm(ConditionalCode);
|
||
|
|
|
||
|
|
// If no false block, then false behavior is fall through and no branch needs
|
||
|
|
// to be inserted.
|
||
|
|
if (!FalseBlock)
|
||
|
|
return 1;
|
||
|
|
|
||
|
|
BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(FalseBlock);
|
||
|
|
return 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB,
|
||
|
|
int *BytesRemoved) const {
|
||
|
|
assert(!BytesRemoved && "code size not handled");
|
||
|
|
|
||
|
|
MachineBasicBlock::iterator Instruction = MBB.end();
|
||
|
|
unsigned Count = 0;
|
||
|
|
|
||
|
|
while (Instruction != MBB.begin()) {
|
||
|
|
--Instruction;
|
||
|
|
if (Instruction->isDebugInstr())
|
||
|
|
continue;
|
||
|
|
if (Instruction->getOpcode() != Lanai::BT &&
|
||
|
|
Instruction->getOpcode() != Lanai::BRCC) {
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Remove the branch.
|
||
|
|
Instruction->eraseFromParent();
|
||
|
|
Instruction = MBB.end();
|
||
|
|
++Count;
|
||
|
|
}
|
||
|
|
|
||
|
|
return Count;
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned LanaiInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
|
||
|
|
int &FrameIndex) const {
|
||
|
|
if (MI.getOpcode() == Lanai::LDW_RI)
|
||
|
|
if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
|
||
|
|
MI.getOperand(2).getImm() == 0) {
|
||
|
|
FrameIndex = MI.getOperand(1).getIndex();
|
||
|
|
return MI.getOperand(0).getReg();
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
|
||
|
|
int &FrameIndex) const {
|
||
|
|
if (MI.getOpcode() == Lanai::LDW_RI) {
|
||
|
|
unsigned Reg;
|
||
|
|
if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
|
||
|
|
return Reg;
|
||
|
|
// Check for post-frame index elimination operations
|
||
|
|
SmallVector<const MachineMemOperand *, 1> Accesses;
|
||
|
|
if (hasLoadFromStackSlot(MI, Accesses)){
|
||
|
|
FrameIndex =
|
||
|
|
cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
|
||
|
|
->getFrameIndex();
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned LanaiInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
|
||
|
|
int &FrameIndex) const {
|
||
|
|
if (MI.getOpcode() == Lanai::SW_RI)
|
||
|
|
if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
|
||
|
|
MI.getOperand(1).getImm() == 0) {
|
||
|
|
FrameIndex = MI.getOperand(0).getIndex();
|
||
|
|
return MI.getOperand(2).getReg();
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool LanaiInstrInfo::getMemOperandWithOffsetWidth(
|
||
|
|
const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
|
||
|
|
unsigned &Width, const TargetRegisterInfo * /*TRI*/) const {
|
||
|
|
// Handle only loads/stores with base register followed by immediate offset
|
||
|
|
// and with add as ALU op.
|
||
|
|
if (LdSt.getNumOperands() != 4)
|
||
|
|
return false;
|
||
|
|
if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() ||
|
||
|
|
!(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
switch (LdSt.getOpcode()) {
|
||
|
|
default:
|
||
|
|
return false;
|
||
|
|
case Lanai::LDW_RI:
|
||
|
|
case Lanai::LDW_RR:
|
||
|
|
case Lanai::SW_RR:
|
||
|
|
case Lanai::SW_RI:
|
||
|
|
Width = 4;
|
||
|
|
break;
|
||
|
|
case Lanai::LDHs_RI:
|
||
|
|
case Lanai::LDHz_RI:
|
||
|
|
case Lanai::STH_RI:
|
||
|
|
Width = 2;
|
||
|
|
break;
|
||
|
|
case Lanai::LDBs_RI:
|
||
|
|
case Lanai::LDBz_RI:
|
||
|
|
case Lanai::STB_RI:
|
||
|
|
Width = 1;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
BaseOp = &LdSt.getOperand(1);
|
||
|
|
Offset = LdSt.getOperand(2).getImm();
|
||
|
|
|
||
|
|
if (!BaseOp->isReg())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool LanaiInstrInfo::getMemOperandsWithOffsetWidth(
|
||
|
|
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
|
||
|
|
int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
|
||
|
|
const TargetRegisterInfo *TRI) const {
|
||
|
|
switch (LdSt.getOpcode()) {
|
||
|
|
default:
|
||
|
|
return false;
|
||
|
|
case Lanai::LDW_RI:
|
||
|
|
case Lanai::LDW_RR:
|
||
|
|
case Lanai::SW_RR:
|
||
|
|
case Lanai::SW_RI:
|
||
|
|
case Lanai::LDHs_RI:
|
||
|
|
case Lanai::LDHz_RI:
|
||
|
|
case Lanai::STH_RI:
|
||
|
|
case Lanai::LDBs_RI:
|
||
|
|
case Lanai::LDBz_RI:
|
||
|
|
const MachineOperand *BaseOp;
|
||
|
|
OffsetIsScalable = false;
|
||
|
|
if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
|
||
|
|
return false;
|
||
|
|
BaseOps.push_back(BaseOp);
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
}
|