519 lines
19 KiB
C++
519 lines
19 KiB
C++
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//===--- Mips.cpp - Tools Implementations -----------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "ToolChains/CommonArgs.h"
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#include "clang/Driver/Driver.h"
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#include "clang/Driver/DriverDiagnostic.h"
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#include "clang/Driver/Options.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/Option/ArgList.h"
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using namespace clang::driver;
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using namespace clang::driver::tools;
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using namespace clang;
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using namespace llvm::opt;
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// Get CPU and ABI names. They are not independent
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// so we have to calculate them together.
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void mips::getMipsCPUAndABI(const ArgList &Args, const llvm::Triple &Triple,
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StringRef &CPUName, StringRef &ABIName) {
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const char *DefMips32CPU = "mips32r2";
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const char *DefMips64CPU = "mips64r2";
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// MIPS32r6 is the default for mips(el)?-img-linux-gnu and MIPS64r6 is the
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// default for mips64(el)?-img-linux-gnu.
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if (Triple.getVendor() == llvm::Triple::ImaginationTechnologies &&
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Triple.isGNUEnvironment()) {
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DefMips32CPU = "mips32r6";
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DefMips64CPU = "mips64r6";
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}
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if (Triple.getSubArch() == llvm::Triple::MipsSubArch_r6) {
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DefMips32CPU = "mips32r6";
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DefMips64CPU = "mips64r6";
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}
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// MIPS64r6 is the default for Android MIPS64 (mips64el-linux-android).
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if (Triple.isAndroid()) {
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DefMips32CPU = "mips32";
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DefMips64CPU = "mips64r6";
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}
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// MIPS3 is the default for mips64*-unknown-openbsd.
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if (Triple.isOSOpenBSD())
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DefMips64CPU = "mips3";
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// MIPS2 is the default for mips(el)?-unknown-freebsd.
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// MIPS3 is the default for mips64(el)?-unknown-freebsd.
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if (Triple.isOSFreeBSD()) {
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DefMips32CPU = "mips2";
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DefMips64CPU = "mips3";
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}
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if (Arg *A = Args.getLastArg(clang::driver::options::OPT_march_EQ,
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options::OPT_mcpu_EQ))
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CPUName = A->getValue();
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if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
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ABIName = A->getValue();
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// Convert a GNU style Mips ABI name to the name
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// accepted by LLVM Mips backend.
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ABIName = llvm::StringSwitch<llvm::StringRef>(ABIName)
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.Case("32", "o32")
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.Case("64", "n64")
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.Default(ABIName);
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}
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// Setup default CPU and ABI names.
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if (CPUName.empty() && ABIName.empty()) {
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switch (Triple.getArch()) {
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default:
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llvm_unreachable("Unexpected triple arch name");
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case llvm::Triple::mips:
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case llvm::Triple::mipsel:
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CPUName = DefMips32CPU;
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break;
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case llvm::Triple::mips64:
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case llvm::Triple::mips64el:
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CPUName = DefMips64CPU;
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break;
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}
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}
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if (ABIName.empty() && (Triple.getEnvironment() == llvm::Triple::GNUABIN32))
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ABIName = "n32";
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if (ABIName.empty() &&
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(Triple.getVendor() == llvm::Triple::MipsTechnologies ||
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Triple.getVendor() == llvm::Triple::ImaginationTechnologies)) {
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ABIName = llvm::StringSwitch<const char *>(CPUName)
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.Case("mips1", "o32")
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.Case("mips2", "o32")
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.Case("mips3", "n64")
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.Case("mips4", "n64")
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.Case("mips5", "n64")
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.Case("mips32", "o32")
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.Case("mips32r2", "o32")
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.Case("mips32r3", "o32")
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.Case("mips32r5", "o32")
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.Case("mips32r6", "o32")
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.Case("mips64", "n64")
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.Case("mips64r2", "n64")
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.Case("mips64r3", "n64")
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.Case("mips64r5", "n64")
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.Case("mips64r6", "n64")
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.Case("octeon", "n64")
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.Case("p5600", "o32")
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.Default("");
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}
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if (ABIName.empty()) {
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// Deduce ABI name from the target triple.
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ABIName = Triple.isMIPS32() ? "o32" : "n64";
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}
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if (CPUName.empty()) {
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// Deduce CPU name from ABI name.
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CPUName = llvm::StringSwitch<const char *>(ABIName)
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.Case("o32", DefMips32CPU)
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.Cases("n32", "n64", DefMips64CPU)
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.Default("");
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}
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// FIXME: Warn on inconsistent use of -march and -mabi.
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}
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std::string mips::getMipsABILibSuffix(const ArgList &Args,
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const llvm::Triple &Triple) {
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StringRef CPUName, ABIName;
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tools::mips::getMipsCPUAndABI(Args, Triple, CPUName, ABIName);
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return llvm::StringSwitch<std::string>(ABIName)
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.Case("o32", "")
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.Case("n32", "32")
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.Case("n64", "64");
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}
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// Convert ABI name to the GNU tools acceptable variant.
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StringRef mips::getGnuCompatibleMipsABIName(StringRef ABI) {
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return llvm::StringSwitch<llvm::StringRef>(ABI)
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.Case("o32", "32")
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.Case("n64", "64")
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.Default(ABI);
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}
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// Select the MIPS float ABI as determined by -msoft-float, -mhard-float,
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// and -mfloat-abi=.
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mips::FloatABI mips::getMipsFloatABI(const Driver &D, const ArgList &Args,
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const llvm::Triple &Triple) {
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mips::FloatABI ABI = mips::FloatABI::Invalid;
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if (Arg *A =
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Args.getLastArg(options::OPT_msoft_float, options::OPT_mhard_float,
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options::OPT_mfloat_abi_EQ)) {
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if (A->getOption().matches(options::OPT_msoft_float))
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ABI = mips::FloatABI::Soft;
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else if (A->getOption().matches(options::OPT_mhard_float))
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ABI = mips::FloatABI::Hard;
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else {
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ABI = llvm::StringSwitch<mips::FloatABI>(A->getValue())
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.Case("soft", mips::FloatABI::Soft)
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.Case("hard", mips::FloatABI::Hard)
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.Default(mips::FloatABI::Invalid);
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if (ABI == mips::FloatABI::Invalid && !StringRef(A->getValue()).empty()) {
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D.Diag(clang::diag::err_drv_invalid_mfloat_abi) << A->getAsString(Args);
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ABI = mips::FloatABI::Hard;
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}
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}
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}
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// If unspecified, choose the default based on the platform.
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if (ABI == mips::FloatABI::Invalid) {
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if (Triple.isOSFreeBSD()) {
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// For FreeBSD, assume "soft" on all flavors of MIPS.
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ABI = mips::FloatABI::Soft;
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} else {
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// Assume "hard", because it's a default value used by gcc.
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// When we start to recognize specific target MIPS processors,
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// we will be able to select the default more correctly.
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ABI = mips::FloatABI::Hard;
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}
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}
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assert(ABI != mips::FloatABI::Invalid && "must select an ABI");
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return ABI;
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}
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void mips::getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple,
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const ArgList &Args,
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std::vector<StringRef> &Features) {
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StringRef CPUName;
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StringRef ABIName;
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getMipsCPUAndABI(Args, Triple, CPUName, ABIName);
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ABIName = getGnuCompatibleMipsABIName(ABIName);
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// Historically, PIC code for MIPS was associated with -mabicalls, a.k.a
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// SVR4 abicalls. Static code does not use SVR4 calling sequences. An ABI
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// extension was developed by Richard Sandiford & Code Sourcery to support
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// static code calling PIC code (CPIC). For O32 and N32 this means we have
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// several combinations of PIC/static and abicalls. Pure static, static
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// with the CPIC extension, and pure PIC code.
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// At final link time, O32 and N32 with CPIC will have another section
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// added to the binary which contains the stub functions to perform
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// any fixups required for PIC code.
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// For N64, the situation is more regular: code can either be static
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// (non-abicalls) or PIC (abicalls). GCC has traditionally picked PIC code
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// code for N64. Since Clang has already built the relocation model portion
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// of the commandline, we pick add +noabicalls feature in the N64 static
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// case.
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// The is another case to be accounted for: -msym32, which enforces that all
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// symbols have 32 bits in size. In this case, N64 can in theory use CPIC
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// but it is unsupported.
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// The combinations for N64 are:
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// a) Static without abicalls and 64bit symbols.
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// b) Static with abicalls and 32bit symbols.
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// c) PIC with abicalls and 64bit symbols.
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// For case (a) we need to add +noabicalls for N64.
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bool IsN64 = ABIName == "64";
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bool IsPIC = false;
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bool NonPIC = false;
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Arg *LastPICArg = Args.getLastArg(options::OPT_fPIC, options::OPT_fno_PIC,
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options::OPT_fpic, options::OPT_fno_pic,
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options::OPT_fPIE, options::OPT_fno_PIE,
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options::OPT_fpie, options::OPT_fno_pie);
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if (LastPICArg) {
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Option O = LastPICArg->getOption();
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NonPIC =
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(O.matches(options::OPT_fno_PIC) || O.matches(options::OPT_fno_pic) ||
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O.matches(options::OPT_fno_PIE) || O.matches(options::OPT_fno_pie));
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IsPIC =
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(O.matches(options::OPT_fPIC) || O.matches(options::OPT_fpic) ||
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O.matches(options::OPT_fPIE) || O.matches(options::OPT_fpie));
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}
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bool UseAbiCalls = false;
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Arg *ABICallsArg =
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Args.getLastArg(options::OPT_mabicalls, options::OPT_mno_abicalls);
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UseAbiCalls =
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!ABICallsArg || ABICallsArg->getOption().matches(options::OPT_mabicalls);
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if (IsN64 && NonPIC && (!ABICallsArg || UseAbiCalls)) {
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D.Diag(diag::warn_drv_unsupported_pic_with_mabicalls)
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<< LastPICArg->getAsString(Args) << (!ABICallsArg ? 0 : 1);
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}
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if (ABICallsArg && !UseAbiCalls && IsPIC) {
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D.Diag(diag::err_drv_unsupported_noabicalls_pic);
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}
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if (!UseAbiCalls)
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Features.push_back("+noabicalls");
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else
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Features.push_back("-noabicalls");
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if (Arg *A = Args.getLastArg(options::OPT_mlong_calls,
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options::OPT_mno_long_calls)) {
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if (A->getOption().matches(options::OPT_mno_long_calls))
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Features.push_back("-long-calls");
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else if (!UseAbiCalls)
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Features.push_back("+long-calls");
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else
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D.Diag(diag::warn_drv_unsupported_longcalls) << (ABICallsArg ? 0 : 1);
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}
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if (Arg *A = Args.getLastArg(options::OPT_mxgot, options::OPT_mno_xgot)) {
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if (A->getOption().matches(options::OPT_mxgot))
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Features.push_back("+xgot");
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else
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Features.push_back("-xgot");
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}
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mips::FloatABI FloatABI = mips::getMipsFloatABI(D, Args, Triple);
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if (FloatABI == mips::FloatABI::Soft) {
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// FIXME: Note, this is a hack. We need to pass the selected float
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// mode to the MipsTargetInfoBase to define appropriate macros there.
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// Now it is the only method.
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Features.push_back("+soft-float");
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}
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if (Arg *A = Args.getLastArg(options::OPT_mnan_EQ)) {
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StringRef Val = StringRef(A->getValue());
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if (Val == "2008") {
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if (mips::getIEEE754Standard(CPUName) & mips::Std2008)
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Features.push_back("+nan2008");
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else {
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Features.push_back("-nan2008");
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D.Diag(diag::warn_target_unsupported_nan2008) << CPUName;
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}
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} else if (Val == "legacy") {
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if (mips::getIEEE754Standard(CPUName) & mips::Legacy)
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Features.push_back("-nan2008");
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else {
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Features.push_back("+nan2008");
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D.Diag(diag::warn_target_unsupported_nanlegacy) << CPUName;
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}
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} else
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D.Diag(diag::err_drv_unsupported_option_argument)
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<< A->getOption().getName() << Val;
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}
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if (Arg *A = Args.getLastArg(options::OPT_mabs_EQ)) {
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StringRef Val = StringRef(A->getValue());
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if (Val == "2008") {
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if (mips::getIEEE754Standard(CPUName) & mips::Std2008) {
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Features.push_back("+abs2008");
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} else {
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Features.push_back("-abs2008");
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D.Diag(diag::warn_target_unsupported_abs2008) << CPUName;
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}
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} else if (Val == "legacy") {
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if (mips::getIEEE754Standard(CPUName) & mips::Legacy) {
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Features.push_back("-abs2008");
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} else {
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Features.push_back("+abs2008");
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D.Diag(diag::warn_target_unsupported_abslegacy) << CPUName;
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}
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} else {
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D.Diag(diag::err_drv_unsupported_option_argument)
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<< A->getOption().getName() << Val;
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}
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}
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AddTargetFeature(Args, Features, options::OPT_msingle_float,
|
||
|
|
options::OPT_mdouble_float, "single-float");
|
||
|
|
AddTargetFeature(Args, Features, options::OPT_mips16, options::OPT_mno_mips16,
|
||
|
|
"mips16");
|
||
|
|
AddTargetFeature(Args, Features, options::OPT_mmicromips,
|
||
|
|
options::OPT_mno_micromips, "micromips");
|
||
|
|
AddTargetFeature(Args, Features, options::OPT_mdsp, options::OPT_mno_dsp,
|
||
|
|
"dsp");
|
||
|
|
AddTargetFeature(Args, Features, options::OPT_mdspr2, options::OPT_mno_dspr2,
|
||
|
|
"dspr2");
|
||
|
|
AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
|
||
|
|
"msa");
|
||
|
|
|
||
|
|
// Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
|
||
|
|
// pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
|
||
|
|
// nooddspreg.
|
||
|
|
if (Arg *A = Args.getLastArg(options::OPT_mfp32, options::OPT_mfpxx,
|
||
|
|
options::OPT_mfp64)) {
|
||
|
|
if (A->getOption().matches(options::OPT_mfp32))
|
||
|
|
Features.push_back("-fp64");
|
||
|
|
else if (A->getOption().matches(options::OPT_mfpxx)) {
|
||
|
|
Features.push_back("+fpxx");
|
||
|
|
Features.push_back("+nooddspreg");
|
||
|
|
} else
|
||
|
|
Features.push_back("+fp64");
|
||
|
|
} else if (mips::shouldUseFPXX(Args, Triple, CPUName, ABIName, FloatABI)) {
|
||
|
|
Features.push_back("+fpxx");
|
||
|
|
Features.push_back("+nooddspreg");
|
||
|
|
} else if (mips::isFP64ADefault(Triple, CPUName)) {
|
||
|
|
Features.push_back("+fp64");
|
||
|
|
Features.push_back("+nooddspreg");
|
||
|
|
}
|
||
|
|
|
||
|
|
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
|
||
|
|
options::OPT_modd_spreg, "nooddspreg");
|
||
|
|
AddTargetFeature(Args, Features, options::OPT_mno_madd4, options::OPT_mmadd4,
|
||
|
|
"nomadd4");
|
||
|
|
AddTargetFeature(Args, Features, options::OPT_mmt, options::OPT_mno_mt, "mt");
|
||
|
|
AddTargetFeature(Args, Features, options::OPT_mcrc, options::OPT_mno_crc,
|
||
|
|
"crc");
|
||
|
|
AddTargetFeature(Args, Features, options::OPT_mvirt, options::OPT_mno_virt,
|
||
|
|
"virt");
|
||
|
|
AddTargetFeature(Args, Features, options::OPT_mginv, options::OPT_mno_ginv,
|
||
|
|
"ginv");
|
||
|
|
|
||
|
|
if (Arg *A = Args.getLastArg(options::OPT_mindirect_jump_EQ)) {
|
||
|
|
StringRef Val = StringRef(A->getValue());
|
||
|
|
if (Val == "hazard") {
|
||
|
|
Arg *B =
|
||
|
|
Args.getLastArg(options::OPT_mmicromips, options::OPT_mno_micromips);
|
||
|
|
Arg *C = Args.getLastArg(options::OPT_mips16, options::OPT_mno_mips16);
|
||
|
|
|
||
|
|
if (B && B->getOption().matches(options::OPT_mmicromips))
|
||
|
|
D.Diag(diag::err_drv_unsupported_indirect_jump_opt)
|
||
|
|
<< "hazard" << "micromips";
|
||
|
|
else if (C && C->getOption().matches(options::OPT_mips16))
|
||
|
|
D.Diag(diag::err_drv_unsupported_indirect_jump_opt)
|
||
|
|
<< "hazard" << "mips16";
|
||
|
|
else if (mips::supportsIndirectJumpHazardBarrier(CPUName))
|
||
|
|
Features.push_back("+use-indirect-jump-hazard");
|
||
|
|
else
|
||
|
|
D.Diag(diag::err_drv_unsupported_indirect_jump_opt)
|
||
|
|
<< "hazard" << CPUName;
|
||
|
|
} else
|
||
|
|
D.Diag(diag::err_drv_unknown_indirect_jump_opt) << Val;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
mips::IEEE754Standard mips::getIEEE754Standard(StringRef &CPU) {
|
||
|
|
// Strictly speaking, mips32r2 and mips64r2 do not conform to the
|
||
|
|
// IEEE754-2008 standard. Support for this standard was first introduced
|
||
|
|
// in Release 3. However, other compilers have traditionally allowed it
|
||
|
|
// for Release 2 so we should do the same.
|
||
|
|
return (IEEE754Standard)llvm::StringSwitch<int>(CPU)
|
||
|
|
.Case("mips1", Legacy)
|
||
|
|
.Case("mips2", Legacy)
|
||
|
|
.Case("mips3", Legacy)
|
||
|
|
.Case("mips4", Legacy)
|
||
|
|
.Case("mips5", Legacy)
|
||
|
|
.Case("mips32", Legacy)
|
||
|
|
.Case("mips32r2", Legacy | Std2008)
|
||
|
|
.Case("mips32r3", Legacy | Std2008)
|
||
|
|
.Case("mips32r5", Legacy | Std2008)
|
||
|
|
.Case("mips32r6", Std2008)
|
||
|
|
.Case("mips64", Legacy)
|
||
|
|
.Case("mips64r2", Legacy | Std2008)
|
||
|
|
.Case("mips64r3", Legacy | Std2008)
|
||
|
|
.Case("mips64r5", Legacy | Std2008)
|
||
|
|
.Case("mips64r6", Std2008)
|
||
|
|
.Default(Std2008);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool mips::hasCompactBranches(StringRef &CPU) {
|
||
|
|
// mips32r6 and mips64r6 have compact branches.
|
||
|
|
return llvm::StringSwitch<bool>(CPU)
|
||
|
|
.Case("mips32r6", true)
|
||
|
|
.Case("mips64r6", true)
|
||
|
|
.Default(false);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool mips::hasMipsAbiArg(const ArgList &Args, const char *Value) {
|
||
|
|
Arg *A = Args.getLastArg(options::OPT_mabi_EQ);
|
||
|
|
return A && (A->getValue() == StringRef(Value));
|
||
|
|
}
|
||
|
|
|
||
|
|
bool mips::isUCLibc(const ArgList &Args) {
|
||
|
|
Arg *A = Args.getLastArg(options::OPT_m_libc_Group);
|
||
|
|
return A && A->getOption().matches(options::OPT_muclibc);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool mips::isNaN2008(const ArgList &Args, const llvm::Triple &Triple) {
|
||
|
|
if (Arg *NaNArg = Args.getLastArg(options::OPT_mnan_EQ))
|
||
|
|
return llvm::StringSwitch<bool>(NaNArg->getValue())
|
||
|
|
.Case("2008", true)
|
||
|
|
.Case("legacy", false)
|
||
|
|
.Default(false);
|
||
|
|
|
||
|
|
// NaN2008 is the default for MIPS32r6/MIPS64r6.
|
||
|
|
return llvm::StringSwitch<bool>(getCPUName(Args, Triple))
|
||
|
|
.Cases("mips32r6", "mips64r6", true)
|
||
|
|
.Default(false);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool mips::isFP64ADefault(const llvm::Triple &Triple, StringRef CPUName) {
|
||
|
|
if (!Triple.isAndroid())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
// Android MIPS32R6 defaults to FP64A.
|
||
|
|
return llvm::StringSwitch<bool>(CPUName)
|
||
|
|
.Case("mips32r6", true)
|
||
|
|
.Default(false);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool mips::isFPXXDefault(const llvm::Triple &Triple, StringRef CPUName,
|
||
|
|
StringRef ABIName, mips::FloatABI FloatABI) {
|
||
|
|
if (Triple.getVendor() != llvm::Triple::ImaginationTechnologies &&
|
||
|
|
Triple.getVendor() != llvm::Triple::MipsTechnologies &&
|
||
|
|
!Triple.isAndroid())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
if (ABIName != "32")
|
||
|
|
return false;
|
||
|
|
|
||
|
|
// FPXX shouldn't be used if either -msoft-float or -mfloat-abi=soft is
|
||
|
|
// present.
|
||
|
|
if (FloatABI == mips::FloatABI::Soft)
|
||
|
|
return false;
|
||
|
|
|
||
|
|
return llvm::StringSwitch<bool>(CPUName)
|
||
|
|
.Cases("mips2", "mips3", "mips4", "mips5", true)
|
||
|
|
.Cases("mips32", "mips32r2", "mips32r3", "mips32r5", true)
|
||
|
|
.Cases("mips64", "mips64r2", "mips64r3", "mips64r5", true)
|
||
|
|
.Default(false);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool mips::shouldUseFPXX(const ArgList &Args, const llvm::Triple &Triple,
|
||
|
|
StringRef CPUName, StringRef ABIName,
|
||
|
|
mips::FloatABI FloatABI) {
|
||
|
|
bool UseFPXX = isFPXXDefault(Triple, CPUName, ABIName, FloatABI);
|
||
|
|
|
||
|
|
// FPXX shouldn't be used if -msingle-float is present.
|
||
|
|
if (Arg *A = Args.getLastArg(options::OPT_msingle_float,
|
||
|
|
options::OPT_mdouble_float))
|
||
|
|
if (A->getOption().matches(options::OPT_msingle_float))
|
||
|
|
UseFPXX = false;
|
||
|
|
|
||
|
|
return UseFPXX;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool mips::supportsIndirectJumpHazardBarrier(StringRef &CPU) {
|
||
|
|
// Supporting the hazard barrier method of dealing with indirect
|
||
|
|
// jumps requires MIPSR2 support.
|
||
|
|
return llvm::StringSwitch<bool>(CPU)
|
||
|
|
.Case("mips32r2", true)
|
||
|
|
.Case("mips32r3", true)
|
||
|
|
.Case("mips32r5", true)
|
||
|
|
.Case("mips32r6", true)
|
||
|
|
.Case("mips64r2", true)
|
||
|
|
.Case("mips64r3", true)
|
||
|
|
.Case("mips64r5", true)
|
||
|
|
.Case("mips64r6", true)
|
||
|
|
.Case("octeon", true)
|
||
|
|
.Case("p5600", true)
|
||
|
|
.Default(false);
|
||
|
|
}
|