67 lines
2.5 KiB
ArmAsm
67 lines
2.5 KiB
ArmAsm
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
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# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5
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ldr w0, 1f
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ldur x0, [sp, #8]
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ldrb w0, [sp], #1
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ldrsh w0, [sp, #2]!
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ldr x0, [sp, #8]
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ldrb w0, [sp, x31]
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ldrsh w0, [sp, x31, lsl #1]
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ldr w0, [sp, w31, sxtw]
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ldr x0, [sp, w31, uxtw #3]
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ldnp w0, w1, [sp, #8]
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ldp x0, x1, [sp], #16
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ldpsw x0, x1, [sp, #8]!
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1:
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# ALL: Iterations: 100
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# ALL-NEXT: Instructions: 1200
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# ALL-NEXT: Total Cycles: 1304
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# M3-NEXT: Total uOps: 1600
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# M4-NEXT: Total uOps: 1400
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# M5-NEXT: Total uOps: 1400
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# ALL: Dispatch Width: 6
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# M3-NEXT: uOps Per Cycle: 1.23
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# M4-NEXT: uOps Per Cycle: 1.07
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# M5-NEXT: uOps Per Cycle: 1.07
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# ALL-NEXT: IPC: 0.92
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# ALL-NEXT: Block RThroughput: 6.0
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# ALL: Instruction Info:
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# ALL-NEXT: [1]: #uOps
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# ALL-NEXT: [2]: Latency
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# ALL-NEXT: [3]: RThroughput
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# ALL-NEXT: [4]: MayLoad
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# ALL-NEXT: [5]: MayStore
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# ALL-NEXT: [6]: HasSideEffects (U)
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# ALL: [1] [2] [3] [4] [5] [6] Instructions:
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# ALL-NEXT: 1 4 0.50 * ldr w0, {{\.?}}Ltmp0
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# ALL-NEXT: 1 4 0.50 * ldur x0, [sp, #8]
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# ALL-NEXT: 1 4 0.50 * ldrb w0, [sp], #1
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# ALL-NEXT: 1 4 0.50 * ldrsh w0, [sp, #2]!
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# ALL-NEXT: 1 4 0.50 * ldr x0, [sp, #8]
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# ALL-NEXT: 1 4 0.50 * ldrb w0, [sp, xzr]
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# ALL-NEXT: 1 5 0.50 * ldrsh w0, [sp, xzr, lsl #1]
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# M3-NEXT: 2 5 0.50 * ldr w0, [sp, wzr, sxtw]
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# M3-NEXT: 2 5 0.50 * ldr x0, [sp, wzr, uxtw #3]
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# M4-NEXT: 1 5 0.50 * ldr w0, [sp, wzr, sxtw]
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# M4-NEXT: 1 5 0.50 * ldr x0, [sp, wzr, uxtw #3]
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# M5-NEXT: 1 5 0.50 * ldr w0, [sp, wzr, sxtw]
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# M5-NEXT: 1 5 0.50 * ldr x0, [sp, wzr, uxtw #3]
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# ALL-NEXT: 1 4 0.50 * ldnp w0, w1, [sp, #8]
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# ALL-NEXT: 2 4 0.50 * ldp x0, x1, [sp], #16
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# ALL-NEXT: 2 4 0.50 * ldpsw x0, x1, [sp, #8]!
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