119 lines
6.2 KiB
ArmAsm
119 lines
6.2 KiB
ArmAsm
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M3
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# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M4
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# RUN: llvm-mca -mtriple=aarch64-linux-gnu -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,M5
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ld2 {v0.s, v1.s}[0], [sp]
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ld2r {v0.2s, v1.2s}, [sp]
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ld2 {v0.2s, v1.2s}, [sp]
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ld2 {v0.d, v1.d}[0], [sp]
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ld2r {v0.2d, v1.2d}, [sp]
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ld2 {v0.2d, v1.2d}, [sp]
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ld2 {v0.s, v1.s}[0], [sp], #8
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ld2r {v0.2s, v1.2s}, [sp], #8
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ld2 {v0.2s, v1.2s}, [sp], #16
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ld2 {v0.d, v1.d}[0], [sp], #16
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ld2r {v0.2d, v1.2d}, [sp], #16
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ld2 {v0.2d, v1.2d}, [sp], #32
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ld2 {v0.s, v1.s}[0], [sp], x0
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ld2r {v0.2s, v1.2s}, [sp], x0
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ld2 {v0.2s, v1.2s}, [sp], x0
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ld2 {v0.d, v1.d}[0], [sp], x0
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ld2r {v0.2d, v1.2d}, [sp], x0
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ld2 {v0.2d, v1.2d}, [sp], x0
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# ALL: Iterations: 100
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# ALL-NEXT: Instructions: 1800
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# M3-NEXT: Total Cycles: 10003
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# M4-NEXT: Total Cycles: 9803
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# M5-NEXT: Total Cycles: 11103
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# ALL-NEXT: Total uOps: 5400
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# ALL: Dispatch Width: 6
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# M3-NEXT: uOps Per Cycle: 0.54
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# M3-NEXT: IPC: 0.18
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# M3-NEXT: Block RThroughput: 42.0
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# M4-NEXT: uOps Per Cycle: 0.55
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# M4-NEXT: IPC: 0.18
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# M4-NEXT: Block RThroughput: 30.0
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# M5-NEXT: uOps Per Cycle: 0.49
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# M5-NEXT: IPC: 0.16
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# M5-NEXT: Block RThroughput: 45.0
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# ALL: Instruction Info:
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# ALL-NEXT: [1]: #uOps
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# ALL-NEXT: [2]: Latency
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# ALL-NEXT: [3]: RThroughput
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# ALL-NEXT: [4]: MayLoad
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# ALL-NEXT: [5]: MayStore
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# ALL-NEXT: [6]: HasSideEffects (U)
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# ALL: [1] [2] [3] [4] [5] [6] Instructions:
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# M3-NEXT: 3 7 1.00 * ld2 { v0.s, v1.s }[0], [sp]
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# M3-NEXT: 2 5 1.00 * ld2r { v0.2s, v1.2s }, [sp]
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# M3-NEXT: 2 10 5.00 * ld2 { v0.2s, v1.2s }, [sp]
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# M3-NEXT: 3 6 1.00 * ld2 { v0.d, v1.d }[0], [sp]
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# M3-NEXT: 2 5 1.00 * ld2r { v0.2d, v1.2d }, [sp]
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# M3-NEXT: 2 10 5.00 * ld2 { v0.2d, v1.2d }, [sp]
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# M3-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], #8
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# M3-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], #8
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# M3-NEXT: 3 10 5.00 * ld2 { v0.2s, v1.2s }, [sp], #16
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# M3-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], #16
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# M3-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], #16
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# M3-NEXT: 3 10 5.00 * ld2 { v0.2d, v1.2d }, [sp], #32
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# M3-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], x0
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# M3-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], x0
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# M3-NEXT: 3 10 5.00 * ld2 { v0.2s, v1.2s }, [sp], x0
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# M3-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], x0
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# M3-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], x0
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# M3-NEXT: 3 10 5.00 * ld2 { v0.2d, v1.2d }, [sp], x0
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# M4-NEXT: 3 6 1.00 * ld2 { v0.s, v1.s }[0], [sp]
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# M4-NEXT: 2 5 1.00 * ld2r { v0.2s, v1.2s }, [sp]
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# M4-NEXT: 2 10 3.00 * ld2 { v0.2s, v1.2s }, [sp]
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# M4-NEXT: 3 6 1.00 * ld2 { v0.d, v1.d }[0], [sp]
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# M4-NEXT: 2 5 1.00 * ld2r { v0.2d, v1.2d }, [sp]
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# M4-NEXT: 2 10 3.00 * ld2 { v0.2d, v1.2d }, [sp]
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# M4-NEXT: 4 6 1.00 * ld2 { v0.s, v1.s }[0], [sp], #8
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# M4-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], #8
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# M4-NEXT: 3 10 3.00 * ld2 { v0.2s, v1.2s }, [sp], #16
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# M4-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], #16
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# M4-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], #16
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# M4-NEXT: 3 10 3.00 * ld2 { v0.2d, v1.2d }, [sp], #32
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# M4-NEXT: 4 6 1.00 * ld2 { v0.s, v1.s }[0], [sp], x0
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# M4-NEXT: 3 5 1.00 * ld2r { v0.2s, v1.2s }, [sp], x0
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# M4-NEXT: 3 10 3.00 * ld2 { v0.2s, v1.2s }, [sp], x0
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# M4-NEXT: 4 6 1.00 * ld2 { v0.d, v1.d }[0], [sp], x0
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# M4-NEXT: 3 5 1.00 * ld2r { v0.2d, v1.2d }, [sp], x0
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# M4-NEXT: 3 10 3.00 * ld2 { v0.2d, v1.2d }, [sp], x0
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# M5-NEXT: 3 7 1.00 * ld2 { v0.s, v1.s }[0], [sp]
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# M5-NEXT: 2 6 1.00 * ld2r { v0.2s, v1.2s }, [sp]
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# M5-NEXT: 2 11 5.50 * ld2 { v0.2s, v1.2s }, [sp]
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# M5-NEXT: 3 7 1.00 * ld2 { v0.d, v1.d }[0], [sp]
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# M5-NEXT: 2 6 1.00 * ld2r { v0.2d, v1.2d }, [sp]
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# M5-NEXT: 2 11 5.50 * ld2 { v0.2d, v1.2d }, [sp]
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# M5-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], #8
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# M5-NEXT: 3 6 1.00 * ld2r { v0.2s, v1.2s }, [sp], #8
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# M5-NEXT: 3 11 5.50 * ld2 { v0.2s, v1.2s }, [sp], #16
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# M5-NEXT: 4 7 1.00 * ld2 { v0.d, v1.d }[0], [sp], #16
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# M5-NEXT: 3 6 1.00 * ld2r { v0.2d, v1.2d }, [sp], #16
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# M5-NEXT: 3 11 5.50 * ld2 { v0.2d, v1.2d }, [sp], #32
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# M5-NEXT: 4 7 1.00 * ld2 { v0.s, v1.s }[0], [sp], x0
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# M5-NEXT: 3 6 1.00 * ld2r { v0.2s, v1.2s }, [sp], x0
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# M5-NEXT: 3 11 5.50 * ld2 { v0.2s, v1.2s }, [sp], x0
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# M5-NEXT: 4 7 1.00 * ld2 { v0.d, v1.d }[0], [sp], x0
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# M5-NEXT: 3 6 1.00 * ld2r { v0.2d, v1.2d }, [sp], x0
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# M5-NEXT: 3 11 5.50 * ld2 { v0.2d, v1.2d }, [sp], x0
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