237 lines
10 KiB
LLVM
237 lines
10 KiB
LLVM
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; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_20 \
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; RUN: | FileCheck %s --check-prefix=PTX
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; RUN: opt < %s -mtriple=nvptx64-nvidia-cuda -S -separate-const-offset-from-gep \
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; RUN: -reassociate-geps-verify-no-dead-code -gvn \
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; RUN: | FileCheck %s --check-prefix=IR
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; Verifies the SeparateConstOffsetFromGEP pass.
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; The following code computes
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; *output = array[x][y] + array[x][y+1] + array[x+1][y] + array[x+1][y+1]
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;
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; We expect SeparateConstOffsetFromGEP to transform it to
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;
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; float *base = &a[x][y];
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; *output = base[0] + base[1] + base[32] + base[33];
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;
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; so the backend can emit PTX that uses fewer virtual registers.
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@array = internal addrspace(3) constant [32 x [32 x float]] zeroinitializer, align 4
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define void @sum_of_array(i32 %x, i32 %y, float* nocapture %output) {
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.preheader:
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%0 = sext i32 %y to i64
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%1 = sext i32 %x to i64
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%2 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
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%3 = addrspacecast float addrspace(3)* %2 to float*
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%4 = load float, float* %3, align 4
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%5 = fadd float %4, 0.000000e+00
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%6 = add i32 %y, 1
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%7 = sext i32 %6 to i64
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%8 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %7
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%9 = addrspacecast float addrspace(3)* %8 to float*
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%10 = load float, float* %9, align 4
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%11 = fadd float %5, %10
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%12 = add i32 %x, 1
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%13 = sext i32 %12 to i64
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%14 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %0
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%15 = addrspacecast float addrspace(3)* %14 to float*
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%16 = load float, float* %15, align 4
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%17 = fadd float %11, %16
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%18 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7
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%19 = addrspacecast float addrspace(3)* %18 to float*
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%20 = load float, float* %19, align 4
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%21 = fadd float %17, %20
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store float %21, float* %output, align 4
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ret void
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}
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; PTX-LABEL: sum_of_array(
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}}
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; IR-LABEL: @sum_of_array(
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; TODO: GVN is unable to preserve the "inbounds" keyword on the first GEP. Need
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; some infrastructure changes to enable such optimizations.
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; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33
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; @sum_of_array2 is very similar to @sum_of_array. The only difference is in
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; the order of "sext" and "add" when computing the array indices. @sum_of_array
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; computes add before sext, e.g., array[sext(x + 1)][sext(y + 1)], while
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; @sum_of_array2 computes sext before add,
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; e.g., array[sext(x) + 1][sext(y) + 1]. SeparateConstOffsetFromGEP should be
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; able to extract constant offsets from both forms.
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define void @sum_of_array2(i32 %x, i32 %y, float* nocapture %output) {
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.preheader:
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%0 = sext i32 %y to i64
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%1 = sext i32 %x to i64
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%2 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
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%3 = addrspacecast float addrspace(3)* %2 to float*
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%4 = load float, float* %3, align 4
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%5 = fadd float %4, 0.000000e+00
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%6 = add i64 %0, 1
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%7 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %6
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%8 = addrspacecast float addrspace(3)* %7 to float*
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%9 = load float, float* %8, align 4
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%10 = fadd float %5, %9
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%11 = add i64 %1, 1
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%12 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %0
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%13 = addrspacecast float addrspace(3)* %12 to float*
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%14 = load float, float* %13, align 4
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%15 = fadd float %10, %14
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%16 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6
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%17 = addrspacecast float addrspace(3)* %16 to float*
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%18 = load float, float* %17, align 4
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%19 = fadd float %15, %18
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store float %19, float* %output, align 4
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ret void
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}
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; PTX-LABEL: sum_of_array2(
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}}
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; IR-LABEL: @sum_of_array2(
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; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33
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; This function loads
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; array[zext(x)][zext(y)]
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; array[zext(x)][zext(y +nuw 1)]
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; array[zext(x +nuw 1)][zext(y)]
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; array[zext(x +nuw 1)][zext(y +nuw 1)].
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;
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; This function is similar to @sum_of_array, but it
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; 1) extends array indices using zext instead of sext;
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; 2) annotates the addition with "nuw"; otherwise, zext(x + 1) => zext(x) + 1
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; may be invalid.
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define void @sum_of_array3(i32 %x, i32 %y, float* nocapture %output) {
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.preheader:
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%0 = zext i32 %y to i64
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%1 = zext i32 %x to i64
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%2 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
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%3 = addrspacecast float addrspace(3)* %2 to float*
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%4 = load float, float* %3, align 4
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%5 = fadd float %4, 0.000000e+00
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%6 = add nuw i32 %y, 1
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%7 = zext i32 %6 to i64
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%8 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %7
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%9 = addrspacecast float addrspace(3)* %8 to float*
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%10 = load float, float* %9, align 4
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%11 = fadd float %5, %10
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%12 = add nuw i32 %x, 1
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%13 = zext i32 %12 to i64
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%14 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %0
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%15 = addrspacecast float addrspace(3)* %14 to float*
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%16 = load float, float* %15, align 4
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%17 = fadd float %11, %16
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%18 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %13, i64 %7
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%19 = addrspacecast float addrspace(3)* %18 to float*
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%20 = load float, float* %19, align 4
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%21 = fadd float %17, %20
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store float %21, float* %output, align 4
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ret void
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}
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; PTX-LABEL: sum_of_array3(
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}}
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; IR-LABEL: @sum_of_array3(
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; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33
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; This function loads
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; array[zext(x)][zext(y)]
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; array[zext(x)][zext(y)]
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; array[zext(x) + 1][zext(y) + 1]
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; array[zext(x) + 1][zext(y) + 1].
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;
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; We expect the generated code to reuse the computation of
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; &array[zext(x)][zext(y)]. See the expected IR and PTX for details.
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define void @sum_of_array4(i32 %x, i32 %y, float* nocapture %output) {
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.preheader:
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%0 = zext i32 %y to i64
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%1 = zext i32 %x to i64
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%2 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %0
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%3 = addrspacecast float addrspace(3)* %2 to float*
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%4 = load float, float* %3, align 4
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%5 = fadd float %4, 0.000000e+00
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%6 = add i64 %0, 1
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%7 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %1, i64 %6
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%8 = addrspacecast float addrspace(3)* %7 to float*
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%9 = load float, float* %8, align 4
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%10 = fadd float %5, %9
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%11 = add i64 %1, 1
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%12 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %0
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%13 = addrspacecast float addrspace(3)* %12 to float*
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%14 = load float, float* %13, align 4
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%15 = fadd float %10, %14
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%16 = getelementptr inbounds [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %11, i64 %6
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%17 = addrspacecast float addrspace(3)* %16 to float*
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%18 = load float, float* %17, align 4
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%19 = fadd float %15, %18
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store float %19, float* %output, align 4
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ret void
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}
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; PTX-LABEL: sum_of_array4(
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}}
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; PTX-DAG: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}}
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; IR-LABEL: @sum_of_array4(
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; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]] addrspace(3)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 1
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 32
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; IR: getelementptr inbounds float, float addrspace(3)* [[BASE_PTR]], i64 33
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; The source code is:
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; p0 = &input[sext(x + y)];
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; p1 = &input[sext(x + (y + 5))];
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;
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; Without reuniting extensions, SeparateConstOffsetFromGEP would emit
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; p0 = &input[sext(x + y)];
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; t1 = &input[sext(x) + sext(y)];
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; p1 = &t1[5];
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;
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; With reuniting extensions, it merges p0 and t1 and thus emits
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; p0 = &input[sext(x + y)];
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; p1 = &p0[5];
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define void @reunion(i32 %x, i32 %y, float* %input) {
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; IR-LABEL: @reunion(
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; PTX-LABEL: reunion(
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entry:
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%xy = add nsw i32 %x, %y
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%0 = sext i32 %xy to i64
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%p0 = getelementptr inbounds float, float* %input, i64 %0
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%v0 = load float, float* %p0, align 4
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; PTX: ld.f32 %f{{[0-9]+}}, {{\[}}[[p0:%rd[0-9]+]]{{\]}}
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call void @use(float %v0)
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%y5 = add nsw i32 %y, 5
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%xy5 = add nsw i32 %x, %y5
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%1 = sext i32 %xy5 to i64
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%p1 = getelementptr inbounds float, float* %input, i64 %1
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; IR: getelementptr inbounds float, float* %p0, i64 5
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%v1 = load float, float* %p1, align 4
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; PTX: ld.f32 %f{{[0-9]+}}, {{\[}}[[p0]]+20{{\]}}
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call void @use(float %v1)
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ret void
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}
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declare void @use(float)
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