269 lines
6.3 KiB
LLVM
269 lines
6.3 KiB
LLVM
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; Test sequences that can use RNSBG.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test a simple mask, which is a wrap-around case.
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define i32 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: rnsbg %r2, %r3, 59, 56, 0
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; CHECK: br %r14
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%orb = or i32 %b, 96
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f2(i64 %a, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: rnsbg %r2, %r3, 59, 56, 0
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; CHECK: br %r14
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%orb = or i64 %b, 96
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case where no wraparound is needed.
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define i32 @f3(i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: rnsbg %r2, %r3, 58, 61, 0
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; CHECK: br %r14
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%orb = or i32 %b, -61
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f4(i64 %a, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK: rnsbg %r2, %r3, 58, 61, 0
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; CHECK: br %r14
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%orb = or i64 %b, -61
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case with just a left shift. This can't use RNSBG.
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define i32 @f6(i32 %a, i32 %b) {
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; CHECK-LABEL: f6:
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; CHECK: sll {{%r[0-5]}}
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; CHECK: nr {{%r[0-5]}}
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; CHECK: br %r14
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%shrb = shl i32 %b, 20
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%and = and i32 %a, %shrb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f7(i64 %a, i64 %b) {
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; CHECK-LABEL: f7:
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; CHECK: sllg {{%r[0-5]}}
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; CHECK: ngr {{%r[0-5]}}
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; CHECK: br %r14
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%shrb = shl i64 %b, 20
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%and = and i64 %a, %shrb
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ret i64 %and
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}
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; Test a case with just a rotate. This can't use RNSBG.
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define i32 @f8(i32 %a, i32 %b) {
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; CHECK-LABEL: f8:
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; CHECK: rll {{%r[0-5]}}
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; CHECK: nr {{%r[0-5]}}
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; CHECK: br %r14
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%shlb = shl i32 %b, 22
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%shrb = lshr i32 %b, 10
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%rotlb = or i32 %shlb, %shrb
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%and = and i32 %a, %rotlb
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ret i32 %and
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}
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; ...and again with i64, which can.
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define i64 @f9(i64 %a, i64 %b) {
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; CHECK-LABEL: f9:
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; CHECK: rnsbg %r2, %r3, 0, 63, 44
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; CHECK: br %r14
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%shlb = shl i64 %b, 44
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%shrb = lshr i64 %b, 20
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%rotlb = or i64 %shlb, %shrb
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%and = and i64 %a, %rotlb
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ret i64 %and
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}
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; Test a case with a left shift and OR, where the OR covers all shifted bits.
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; We can do the whole thing using RNSBG.
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define i32 @f10(i32 %a, i32 %b) {
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; CHECK-LABEL: f10:
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; CHECK: rnsbg %r2, %r3, 32, 56, 7
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; CHECK: br %r14
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%shlb = shl i32 %b, 7
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%orb = or i32 %shlb, 127
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f11(i64 %a, i64 %b) {
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; CHECK-LABEL: f11:
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; CHECK: rnsbg %r2, %r3, 0, 56, 7
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; CHECK: br %r14
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%shlb = shl i64 %b, 7
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%orb = or i64 %shlb, 127
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case with a left shift and OR, where the OR doesn't cover all
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; shifted bits. We can't use RNSBG for the shift, but we can for the OR
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; and AND.
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define i32 @f12(i32 %a, i32 %b) {
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; CHECK-LABEL: f12:
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; CHECK: sll %r3, 7
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; CHECK: rnsbg %r2, %r3, 32, 57, 0
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; CHECK: br %r14
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%shlb = shl i32 %b, 7
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%orb = or i32 %shlb, 63
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f13(i64 %a, i64 %b) {
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; CHECK-LABEL: f13:
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; CHECK: sllg [[REG:%r[01345]]], %r3, 7
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; CHECK: rnsbg %r2, [[REG]], 0, 57, 0
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; CHECK: br %r14
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%shlb = shl i64 %b, 7
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%orb = or i64 %shlb, 63
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case with a right shift and OR, where the OR covers all the shifted
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; bits. The whole thing can be done using RNSBG.
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define i32 @f14(i32 %a, i32 %b) {
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; CHECK-LABEL: f14:
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; CHECK: rnsbg %r2, %r3, 60, 63, 37
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; CHECK: br %r14
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%shrb = lshr i32 %b, 27
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%orb = or i32 %shrb, -16
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f15(i64 %a, i64 %b) {
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; CHECK-LABEL: f15:
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; CHECK: rnsbg %r2, %r3, 60, 63, 5
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; CHECK: br %r14
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%shrb = lshr i64 %b, 59
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%orb = or i64 %shrb, -16
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case with a right shift and OR, where the OR doesn't cover all the
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; shifted bits. The shift needs to be done separately, but the OR and AND
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; can use RNSBG.
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define i32 @f16(i32 %a, i32 %b) {
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; CHECK-LABEL: f16:
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; CHECK: srl %r3, 29
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; CHECK: rnsbg %r2, %r3, 60, 63, 0
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; CHECK: br %r14
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%shrb = lshr i32 %b, 29
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%orb = or i32 %shrb, -16
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f17(i64 %a, i64 %b) {
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; CHECK-LABEL: f17:
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; CHECK: srlg [[REG:%r[01345]]], %r3, 61
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; CHECK: rnsbg %r2, [[REG]], 60, 63, 0
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; CHECK: br %r14
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%shrb = lshr i64 %b, 61
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%orb = or i64 %shrb, -16
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a combination involving an ASHR in which the sign bits matter.
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; We can't use RNSBG for the ASHR in that case, but we can for the rest.
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define i32 @f18(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f18:
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; CHECK: sra %r3, 4
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; CHECK: rnsbg %r2, %r3, 32, 62, 1
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; CHECK: br %r14
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%ashrb = ashr i32 %b, 4
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store i32 %ashrb, i32 *%dest
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%shlb = shl i32 %ashrb, 1
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%orb = or i32 %shlb, 1
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f19(i64 %a, i64 %b, i64 *%dest) {
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; CHECK-LABEL: f19:
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; CHECK: srag [[REG:%r[0145]]], %r3, 34
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; CHECK: rnsbg %r2, [[REG]], 0, 62, 1
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; CHECK: br %r14
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%ashrb = ashr i64 %b, 34
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store i64 %ashrb, i64 *%dest
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%shlb = shl i64 %ashrb, 1
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%orb = or i64 %shlb, 1
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a combination involving an ASHR in which the sign bits don't matter.
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define i32 @f20(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f20:
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; CHECK: rnsbg %r2, %r3, 48, 62, 48
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; CHECK: br %r14
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%ashrb = ashr i32 %b, 17
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store i32 %ashrb, i32 *%dest
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%shlb = shl i32 %ashrb, 1
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%orb = or i32 %shlb, -65535
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%and = and i32 %a, %orb
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ret i32 %and
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}
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; ...and again with i64.
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define i64 @f21(i64 %a, i64 %b, i64 *%dest) {
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; CHECK-LABEL: f21:
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; CHECK: rnsbg %r2, %r3, 48, 62, 16
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; CHECK: br %r14
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%ashrb = ashr i64 %b, 49
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store i64 %ashrb, i64 *%dest
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%shlb = shl i64 %ashrb, 1
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%orb = or i64 %shlb, -65535
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%and = and i64 %a, %orb
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ret i64 %and
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}
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; Test a case with a shift, OR, and rotate where the OR covers all shifted bits.
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define i64 @f22(i64 %a, i64 %b) {
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; CHECK-LABEL: f22:
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; CHECK: rnsbg %r2, %r3, 60, 54, 9
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; CHECK: br %r14
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%shlb = shl i64 %b, 5
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%orb = or i64 %shlb, 31
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%shlorb = shl i64 %orb, 4
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%shrorb = lshr i64 %orb, 60
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%rotlorb = or i64 %shlorb, %shrorb
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%and = and i64 %a, %rotlorb
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ret i64 %and
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}
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; Check the handling of zext and AND, which isn't suitable for RNSBG.
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define i64 @f23(i64 %a, i32 %b) {
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; CHECK-LABEL: f23:
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; CHECK-NOT: rnsbg
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; CHECK: br %r14
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%add = add i32 %b, 1
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%ext = zext i32 %add to i64
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%and = and i64 %a, %ext
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ret i64 %and
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}
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