37 lines
1.3 KiB
LLVM
37 lines
1.3 KiB
LLVM
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; RUN: llc -march=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s
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target triple = "hexagon"
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; Test the the store mask is adjusted for gaps between sections. The
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; Vector Combine pass generates masked stores for chunks of 128 bytes.
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; The masked store must be shifted if the first store in a section
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; is not a multiple of 128 bytes. This test checks that two masks
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; are created, and the second mask is used in a masked store.
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; CHECK: [[REG:r[0-9]+]] = ##.LCPI0_1
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; CHECK: [[VREG1:v[0-9]+]] = vmem([[REG]]+#0)
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; CHECK: [[VREG2:v[0-9]+]] = vlalign([[VREG1]],v{{[0-9]+}},r{{[0-9]+}})
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; CHECK: [[QREG:q[0-3]+]] = vand([[VREG2]],r{{[0-9]+}})
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; CHECK: if ([[QREG]]) vmem({{.*}}) = v{{[0-9]+}}
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define dllexport void @f0(i32* %a0) local_unnamed_addr #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = or i32 -1, 40
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%v1 = getelementptr inbounds i32, i32* %a0, i32 %v0
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%v2 = bitcast i32* %v1 to <8 x i32>*
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store <8 x i32> undef, <8 x i32>* %v2, align 32
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%v3 = or i32 0, 48
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%v4 = getelementptr inbounds i32, i32* %a0, i32 %v3
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%v5 = bitcast i32* %v4 to <8 x i32>*
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store <8 x i32> undef, <8 x i32>* %v5, align 64
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br i1 undef, label %b2, label %b1
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b2: ; preds = %b1
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ret void
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}
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attributes #0 = { "target-features"="+hvxv66,+hvx-length128b" }
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