23 lines
1.3 KiB
LLVM
23 lines
1.3 KiB
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that this compiles successfully.
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; CHECK: vsplat
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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define void @fred(<64 x i8>* %a0) #0 {
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b0:
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%v1 = load <64 x i8>, <64 x i8>* %a0, align 8
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%v2 = zext <64 x i8> %v1 to <64 x i32>
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%v3 = add nuw nsw <64 x i32> %v2, zeroinitializer
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%v4 = icmp ugt <64 x i32> %v3, <i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254>
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%v5 = zext <64 x i1> %v4 to <64 x i32>
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%v6 = add nuw nsw <64 x i32> %v3, %v5
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%v7 = trunc <64 x i32> %v6 to <64 x i8>
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store <64 x i8> %v7, <64 x i8>* %a0, align 8
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
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