27 lines
973 B
LLVM
27 lines
973 B
LLVM
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; RUN: llc -march=hexagon -disable-packetizer -hexagon-align-loads < %s | FileCheck %s
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; CHECK-LABEL: test_00:
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; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
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; CHECK-DAG: v[[V01:[0-9]+]] = vmem(r[[B00]]+#1)
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; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])
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define void @test_00(<64 x i8>* %p, <64 x i8>* %q) #0 {
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%v0 = load <64 x i8>, <64 x i8>* %p, align 1
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store <64 x i8> %v0, <64 x i8>* %q, align 1
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ret void
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}
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; CHECK-LABEL: test_01:
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; CHECK-DAG: v[[V10:[0-9]+]] = vmem(r[[B01:[0-9]+]]+#0)
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; CHECK-DAG: v[[V11:[0-9]+]] = vmem(r[[B01]]+#1)
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; CHECK-DAG: v[[V12:[0-9]+]] = vmem(r[[B01]]+#2)
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; CHECK: }
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; CHECK-DAG: valign(v[[V11]],v[[V10]],r[[B01]])
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; CHECK-DAG: valign(v[[V12]],v[[V11]],r[[B01]])
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define void @test_01(<128 x i8>* %p, <128 x i8>* %q) #0 {
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%v0 = load <128 x i8>, <128 x i8>* %p, align 1
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store <128 x i8> %v0, <128 x i8>* %q, align 1
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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