40 lines
1.6 KiB
LLVM
40 lines
1.6 KiB
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; The generation of a constant vector in the selection step resulted in
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; a VSPLAT, which, deeper in the expression tree had an unrelated BITCAST.
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; That bitcast was erroneously removed by the constant vector selection
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; function, and caused a selection error due to a type mismatch.
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;
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; Make sure this compiles successfully.
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; CHECK: vsplat
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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@g0 = global <8 x i16> zeroinitializer, align 2
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define i32 @fred() #0 {
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b0:
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%v1 = load <8 x i16>, <8 x i16>* @g0, align 2
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%v2 = icmp sgt <8 x i16> %v1, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
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%v3 = zext <8 x i1> %v2 to <8 x i32>
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%v4 = add nuw nsw <8 x i32> zeroinitializer, %v3
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%v5 = add nuw nsw <8 x i32> %v4, zeroinitializer
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%v6 = shufflevector <8 x i32> %v5, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%v7 = add nuw nsw <8 x i32> %v5, %v6
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%v8 = extractelement <8 x i32> %v7, i32 0
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%v9 = add nuw nsw i32 %v8, 0
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%v10 = add nuw nsw i32 %v9, 0
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%v11 = add nuw nsw i32 %v10, 0
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%v12 = icmp ult i32 %v11, 5
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br i1 %v12, label %b13, label %b14
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b13: ; preds = %b0
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ret i32 %v11
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b14: ; preds = %b0
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ret i32 0
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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