60 lines
2.1 KiB
TableGen
60 lines
2.1 KiB
TableGen
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//===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel TSX instruction
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// set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// TSX instructions
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def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>,
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[SDNPHasChain, SDNPSideEffect]>;
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let SchedRW = [WriteSystem] in {
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let usesCustomInserter = 1 in
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def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
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"# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>,
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Requires<[HasRTM]>;
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let isBranch = 1, isTerminator = 1, Defs = [EAX] in {
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def XBEGIN_2 : Ii16PCRel<0xc7, MRM_F8, (outs), (ins brtarget16:$dst),
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"xbegin\t$dst", []>, OpSize16;
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def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst),
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"xbegin\t$dst", []>, OpSize32;
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}
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// Pseudo instruction to fake the definition of EAX on the fallback code path.
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let isPseudo = 1, Defs = [EAX] in {
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def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>;
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}
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def XEND : I<0x01, MRM_D5, (outs), (ins),
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"xend", [(int_x86_xend)]>, PS, Requires<[HasRTM]>;
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let Defs = [EFLAGS] in
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def XTEST : I<0x01, MRM_D6, (outs), (ins),
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"xtest", [(set EFLAGS, (X86xtest))]>, PS, Requires<[HasRTM]>;
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def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
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"xabort\t$imm",
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[(int_x86_xabort timm:$imm)]>, Requires<[HasRTM]>;
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} // SchedRW
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// HLE prefixes
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let SchedRW = [WriteSystem] in {
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let isAsmParserOnly = 1 in {
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def XACQUIRE_PREFIX : I<0xF2, PrefixByte, (outs), (ins), "xacquire", []>;
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def XRELEASE_PREFIX : I<0xF3, PrefixByte, (outs), (ins), "xrelease", []>;
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}
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} // SchedRW
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