97 lines
3.6 KiB
C++
97 lines
3.6 KiB
C++
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//===- MipsOptionRecord.cpp - Abstraction for storing information ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MipsOptionRecord.h"
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#include "MipsABIInfo.h"
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#include "MipsELFStreamer.h"
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#include "MipsTargetStreamer.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSectionELF.h"
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#include <cassert>
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using namespace llvm;
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void MipsRegInfoRecord::EmitMipsOptionRecord() {
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MCAssembler &MCA = Streamer->getAssembler();
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MipsTargetStreamer *MTS =
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static_cast<MipsTargetStreamer *>(Streamer->getTargetStreamer());
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Streamer->PushSection();
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// We need to distinguish between N64 and the rest because at the moment
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// we don't emit .Mips.options for other ELFs other than N64.
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// Since .reginfo has the same information as .Mips.options (ODK_REGINFO),
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// we can use the same abstraction (MipsRegInfoRecord class) to handle both.
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if (MTS->getABI().IsN64()) {
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// The EntrySize value of 1 seems strange since the records are neither
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// 1-byte long nor fixed length but it matches the value GAS emits.
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MCSectionELF *Sec =
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Context.getELFSection(".MIPS.options", ELF::SHT_MIPS_OPTIONS,
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ELF::SHF_ALLOC | ELF::SHF_MIPS_NOSTRIP, 1, "");
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MCA.registerSection(*Sec);
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Sec->setAlignment(Align(8));
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Streamer->SwitchSection(Sec);
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Streamer->emitInt8(ELF::ODK_REGINFO); // kind
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Streamer->emitInt8(40); // size
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Streamer->emitInt16(0); // section
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Streamer->emitInt32(0); // info
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Streamer->emitInt32(ri_gprmask);
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Streamer->emitInt32(0); // pad
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Streamer->emitInt32(ri_cprmask[0]);
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Streamer->emitInt32(ri_cprmask[1]);
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Streamer->emitInt32(ri_cprmask[2]);
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Streamer->emitInt32(ri_cprmask[3]);
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Streamer->emitIntValue(ri_gp_value, 8);
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} else {
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MCSectionELF *Sec = Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO,
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ELF::SHF_ALLOC, 24, "");
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MCA.registerSection(*Sec);
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Sec->setAlignment(MTS->getABI().IsN32() ? Align(8) : Align(4));
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Streamer->SwitchSection(Sec);
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Streamer->emitInt32(ri_gprmask);
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Streamer->emitInt32(ri_cprmask[0]);
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Streamer->emitInt32(ri_cprmask[1]);
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Streamer->emitInt32(ri_cprmask[2]);
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Streamer->emitInt32(ri_cprmask[3]);
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assert((ri_gp_value & 0xffffffff) == ri_gp_value);
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Streamer->emitInt32(ri_gp_value);
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}
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Streamer->PopSection();
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}
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void MipsRegInfoRecord::SetPhysRegUsed(unsigned Reg,
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const MCRegisterInfo *MCRegInfo) {
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unsigned Value = 0;
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for (const MCPhysReg &SubReg : MCRegInfo->subregs_inclusive(Reg)) {
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unsigned EncVal = MCRegInfo->getEncodingValue(SubReg);
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Value |= 1 << EncVal;
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if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg))
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ri_gprmask |= Value;
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else if (COP0RegClass->contains(SubReg))
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ri_cprmask[0] |= Value;
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// MIPS COP1 is the FPU.
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else if (FGR32RegClass->contains(SubReg) ||
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FGR64RegClass->contains(SubReg) ||
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AFGR64RegClass->contains(SubReg) ||
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MSA128BRegClass->contains(SubReg))
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ri_cprmask[1] |= Value;
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else if (COP2RegClass->contains(SubReg))
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ri_cprmask[2] |= Value;
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else if (COP3RegClass->contains(SubReg))
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ri_cprmask[3] |= Value;
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}
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}
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