120 lines
4.0 KiB
C
120 lines
4.0 KiB
C
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//===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Hexagon specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include <cstdint>
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#include <string>
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#define Hexagon_POINTER_SIZE 4
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#define Hexagon_PointerSize (Hexagon_POINTER_SIZE)
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#define Hexagon_PointerSize_Bits (Hexagon_POINTER_SIZE * 8)
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#define Hexagon_WordSize Hexagon_PointerSize
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#define Hexagon_WordSize_Bits Hexagon_PointerSize_Bits
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// allocframe saves LR and FP on stack before allocating
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// a new stack frame. This takes 8 bytes.
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#define HEXAGON_LRFP_SIZE 8
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// Normal instruction size (in bytes).
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#define HEXAGON_INSTR_SIZE 4
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// Maximum number of words and instructions in a packet.
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#define HEXAGON_PACKET_SIZE 4
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#define HEXAGON_MAX_PACKET_SIZE (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE)
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// Minimum number of instructions in an end-loop packet.
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#define HEXAGON_PACKET_INNER_SIZE 2
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#define HEXAGON_PACKET_OUTER_SIZE 3
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// Maximum number of instructions in a packet before shuffling,
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// including a compound one or a duplex or an extender.
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#define HEXAGON_PRESHUFFLE_PACKET_SIZE (HEXAGON_PACKET_SIZE + 3)
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// Name of the global offset table as defined by the Hexagon ABI
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#define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_"
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namespace llvm {
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struct InstrStage;
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class FeatureBitset;
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectTargetWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class MCTargetOptions;
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class Target;
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class Triple;
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class StringRef;
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extern cl::opt<bool> HexagonDisableCompound;
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extern cl::opt<bool> HexagonDisableDuplex;
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extern const InstrStage HexagonStages[];
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MCInstrInfo *createHexagonMCInstrInfo();
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MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT);
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namespace Hexagon_MC {
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StringRef selectHexagonCPU(StringRef CPU);
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FeatureBitset completeHVXFeatures(const FeatureBitset &FB);
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/// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser,
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/// etc. do not need to go through TargetRegistry.
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MCSubtargetInfo *createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU,
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StringRef FS);
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MCSubtargetInfo const *getArchSubtarget(MCSubtargetInfo const *STI);
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void addArchSubtarget(MCSubtargetInfo const *STI,
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StringRef FS);
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unsigned GetELFFlags(const MCSubtargetInfo &STI);
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llvm::ArrayRef<MCPhysReg> GetVectRegRev();
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}
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MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &MCT);
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MCAsmBackend *createHexagonAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options);
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std::unique_ptr<MCObjectTargetWriter>
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createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU);
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unsigned HexagonGetLastSlot();
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unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes);
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} // End llvm namespace
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// Define symbolic names for Hexagon registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "HexagonGenRegisterInfo.inc"
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// Defines symbolic names for the Hexagon instructions.
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//
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#define GET_INSTRINFO_ENUM
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#define GET_INSTRINFO_SCHED_ENUM
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#include "HexagonGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "HexagonGenSubtargetInfo.inc"
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#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
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