624 lines
21 KiB
C++
624 lines
21 KiB
C++
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//===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Hexagon specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonArch.h"
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#include "HexagonTargetStreamer.h"
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#include "MCTargetDesc/HexagonInstPrinter.h"
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#include "MCTargetDesc/HexagonMCAsmInfo.h"
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#include "MCTargetDesc/HexagonMCELFStreamer.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "TargetInfo/HexagonTargetInfo.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDwarf.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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#include <mutex>
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#include <new>
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#include <string>
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#include <unordered_map>
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "HexagonGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "HexagonGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "HexagonGenRegisterInfo.inc"
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cl::opt<bool> llvm::HexagonDisableCompound
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("mno-compound",
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cl::desc("Disable looking for compound instructions for Hexagon"));
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cl::opt<bool> llvm::HexagonDisableDuplex
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("mno-pairing",
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cl::desc("Disable looking for duplex instructions for Hexagon"));
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namespace { // These flags are to be deprecated
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cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
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cl::init(false));
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cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
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cl::init(false));
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cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
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cl::init(false));
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cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
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cl::init(false));
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cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
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cl::init(false));
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cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
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cl::init(false));
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cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
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cl::init(false));
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cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"),
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cl::init(false));
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cl::opt<Hexagon::ArchEnum>
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EnableHVX("mhvx",
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cl::desc("Enable Hexagon Vector eXtensions"),
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cl::values(
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clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
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clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
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clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
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clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
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clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
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// Sentinel for no value specified.
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clEnumValN(Hexagon::ArchEnum::Generic, "", "")),
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// Sentinel for flag not present.
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cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional);
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} // namespace
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static cl::opt<bool>
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DisableHVX("mno-hvx", cl::Hidden,
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cl::desc("Disable Hexagon Vector eXtensions"));
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static StringRef DefaultArch = "hexagonv60";
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static StringRef HexagonGetArchVariant() {
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if (MV5)
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return "hexagonv5";
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if (MV55)
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return "hexagonv55";
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if (MV60)
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return "hexagonv60";
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if (MV62)
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return "hexagonv62";
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if (MV65)
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return "hexagonv65";
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if (MV66)
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return "hexagonv66";
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if (MV67)
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return "hexagonv67";
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if (MV67T)
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return "hexagonv67t";
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return "";
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}
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StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) {
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StringRef ArchV = HexagonGetArchVariant();
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if (!ArchV.empty() && !CPU.empty()) {
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// Tiny cores have a "t" suffix that is discarded when creating a secondary
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// non-tiny subtarget. See: addArchSubtarget
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std::pair<StringRef,StringRef> ArchP = ArchV.split('t');
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std::pair<StringRef,StringRef> CPUP = CPU.split('t');
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if (!ArchP.first.equals(CPUP.first))
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report_fatal_error("conflicting architectures specified.");
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return CPU;
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}
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if (ArchV.empty()) {
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if (CPU.empty())
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CPU = DefaultArch;
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return CPU;
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}
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return ArchV;
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}
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unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
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unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) {
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enum {
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CVI_NONE = 0,
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CVI_XLANE = 1 << 0,
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CVI_SHIFT = 1 << 1,
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CVI_MPY0 = 1 << 2,
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CVI_MPY1 = 1 << 3,
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CVI_ZW = 1 << 4
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};
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if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL ||
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ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM)
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return (*Lanes = 4, CVI_XLANE);
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else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 &&
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ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
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return (*Lanes = 2, CVI_XLANE | CVI_MPY0);
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else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01)
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return (*Lanes = 2, CVI_MPY0);
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else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
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return (*Lanes = 2, CVI_XLANE);
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else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
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ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT &&
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ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
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ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
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return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1);
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else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
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ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT)
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return (*Lanes = 1, CVI_XLANE | CVI_SHIFT);
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else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
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ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
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return (*Lanes = 1, CVI_MPY0 | CVI_MPY1);
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else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW)
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return (*Lanes = 1, CVI_ZW);
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else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE)
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return (*Lanes = 1, CVI_XLANE);
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else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT)
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return (*Lanes = 1, CVI_SHIFT);
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return (*Lanes = 0, CVI_NONE);
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}
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namespace llvm {
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namespace HexagonFUnits {
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bool isSlot0Only(unsigned units) {
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return HexagonItinerariesV62FU::SLOT0 == units;
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}
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} // namespace HexagonFUnits
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} // namespace llvm
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namespace {
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class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
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public:
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HexagonTargetAsmStreamer(MCStreamer &S,
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formatted_raw_ostream &OS,
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bool isVerboseAsm,
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MCInstPrinter &IP)
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: HexagonTargetStreamer(S) {}
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void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
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const MCInst &Inst, const MCSubtargetInfo &STI,
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raw_ostream &OS) override {
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assert(HexagonMCInstrInfo::isBundle(Inst));
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assert(HexagonMCInstrInfo::bundleSize(Inst) <= HEXAGON_PACKET_SIZE);
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std::string Buffer;
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{
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raw_string_ostream TempStream(Buffer);
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InstPrinter.printInst(&Inst, Address, "", STI, TempStream);
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}
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StringRef Contents(Buffer);
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auto PacketBundle = Contents.rsplit('\n');
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auto HeadTail = PacketBundle.first.split('\n');
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StringRef Separator = "\n";
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StringRef Indent = "\t";
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OS << "\t{\n";
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while (!HeadTail.first.empty()) {
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StringRef InstTxt;
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auto Duplex = HeadTail.first.split('\v');
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if (!Duplex.second.empty()) {
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OS << Indent << Duplex.first << Separator;
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InstTxt = Duplex.second;
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} else if (!HeadTail.first.trim().startswith("immext")) {
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InstTxt = Duplex.first;
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}
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if (!InstTxt.empty())
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OS << Indent << InstTxt << Separator;
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HeadTail = HeadTail.second.split('\n');
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}
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if (HexagonMCInstrInfo::isMemReorderDisabled(Inst))
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OS << "\n\t} :mem_noshuf" << PacketBundle.second;
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else
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OS << "\t}" << PacketBundle.second;
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}
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};
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class HexagonTargetELFStreamer : public HexagonTargetStreamer {
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public:
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MCELFStreamer &getStreamer() {
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return static_cast<MCELFStreamer &>(Streamer);
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}
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HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
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: HexagonTargetStreamer(S) {
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MCAssembler &MCA = getStreamer().getAssembler();
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MCA.setELFHeaderEFlags(Hexagon_MC::GetELFFlags(STI));
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}
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void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
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unsigned ByteAlignment,
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unsigned AccessSize) override {
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HexagonMCELFStreamer &HexagonELFStreamer =
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static_cast<HexagonMCELFStreamer &>(getStreamer());
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HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
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AccessSize);
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}
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void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
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unsigned ByteAlignment,
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unsigned AccessSize) override {
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HexagonMCELFStreamer &HexagonELFStreamer =
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static_cast<HexagonMCELFStreamer &>(getStreamer());
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HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
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Symbol, Size, ByteAlignment, AccessSize);
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}
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};
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} // end anonymous namespace
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llvm::MCInstrInfo *llvm::createHexagonMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitHexagonMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitHexagonMCRegisterInfo(X, Hexagon::R31);
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return X;
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}
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static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT,
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const MCTargetOptions &Options) {
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MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
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// VirtualFP = (R30 + #0).
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MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
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nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI)
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{
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if (SyntaxVariant == 0)
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return new HexagonInstPrinter(MAI, MII, MRI);
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else
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return nullptr;
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}
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static MCTargetStreamer *
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createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
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MCInstPrinter *IP, bool IsVerboseAsm) {
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return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP);
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}
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static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
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std::unique_ptr<MCAsmBackend> &&MAB,
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std::unique_ptr<MCObjectWriter> &&OW,
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std::unique_ptr<MCCodeEmitter> &&Emitter,
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bool RelaxAll) {
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return createHexagonELFStreamer(T, Context, std::move(MAB), std::move(OW),
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std::move(Emitter));
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}
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static MCTargetStreamer *
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createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
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return new HexagonTargetELFStreamer(S, STI);
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}
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static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo* STI, uint64_t F) {
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if (STI->getFeatureBits()[F])
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STI->ToggleFeature(F);
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}
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static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo* STI, uint64_t F) {
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return STI->getFeatureBits()[F];
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}
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||
|
|
|
||
|
|
namespace {
|
||
|
|
std::string selectHexagonFS(StringRef CPU, StringRef FS) {
|
||
|
|
SmallVector<StringRef, 3> Result;
|
||
|
|
if (!FS.empty())
|
||
|
|
Result.push_back(FS);
|
||
|
|
|
||
|
|
switch (EnableHVX) {
|
||
|
|
case Hexagon::ArchEnum::V5:
|
||
|
|
case Hexagon::ArchEnum::V55:
|
||
|
|
break;
|
||
|
|
case Hexagon::ArchEnum::V60:
|
||
|
|
Result.push_back("+hvxv60");
|
||
|
|
break;
|
||
|
|
case Hexagon::ArchEnum::V62:
|
||
|
|
Result.push_back("+hvxv62");
|
||
|
|
break;
|
||
|
|
case Hexagon::ArchEnum::V65:
|
||
|
|
Result.push_back("+hvxv65");
|
||
|
|
break;
|
||
|
|
case Hexagon::ArchEnum::V66:
|
||
|
|
Result.push_back("+hvxv66");
|
||
|
|
break;
|
||
|
|
case Hexagon::ArchEnum::V67:
|
||
|
|
Result.push_back("+hvxv67");
|
||
|
|
break;
|
||
|
|
case Hexagon::ArchEnum::Generic:{
|
||
|
|
Result.push_back(StringSwitch<StringRef>(CPU)
|
||
|
|
.Case("hexagonv60", "+hvxv60")
|
||
|
|
.Case("hexagonv62", "+hvxv62")
|
||
|
|
.Case("hexagonv65", "+hvxv65")
|
||
|
|
.Case("hexagonv66", "+hvxv66")
|
||
|
|
.Case("hexagonv67", "+hvxv67")
|
||
|
|
.Case("hexagonv67t", "+hvxv67"));
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
case Hexagon::ArchEnum::NoArch:
|
||
|
|
// Sentinel if -mhvx isn't specified
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
return join(Result.begin(), Result.end(), ",");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool isCPUValid(const std::string &CPU) {
|
||
|
|
return Hexagon::CpuTable.find(CPU) != Hexagon::CpuTable.cend();
|
||
|
|
}
|
||
|
|
|
||
|
|
namespace {
|
||
|
|
std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
|
||
|
|
StringRef FS) {
|
||
|
|
std::pair<std::string, std::string> Result;
|
||
|
|
Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU));
|
||
|
|
Result.second = selectHexagonFS(Result.first, FS);
|
||
|
|
return Result;
|
||
|
|
}
|
||
|
|
std::mutex ArchSubtargetMutex;
|
||
|
|
std::unordered_map<std::string, std::unique_ptr<MCSubtargetInfo const>>
|
||
|
|
ArchSubtarget;
|
||
|
|
} // namespace
|
||
|
|
|
||
|
|
MCSubtargetInfo const *
|
||
|
|
Hexagon_MC::getArchSubtarget(MCSubtargetInfo const *STI) {
|
||
|
|
std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
|
||
|
|
auto Existing = ArchSubtarget.find(std::string(STI->getCPU()));
|
||
|
|
if (Existing == ArchSubtarget.end())
|
||
|
|
return nullptr;
|
||
|
|
return Existing->second.get();
|
||
|
|
}
|
||
|
|
|
||
|
|
FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
|
||
|
|
using namespace Hexagon;
|
||
|
|
// Make sure that +hvx-length turns hvx on, and that "hvx" alone
|
||
|
|
// turns on hvxvNN, corresponding to the existing ArchVNN.
|
||
|
|
FeatureBitset FB = S;
|
||
|
|
unsigned CpuArch = ArchV5;
|
||
|
|
for (unsigned F : {ArchV67, ArchV66, ArchV65, ArchV62, ArchV60, ArchV55,
|
||
|
|
ArchV5}) {
|
||
|
|
if (!FB.test(F))
|
||
|
|
continue;
|
||
|
|
CpuArch = F;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
bool UseHvx = false;
|
||
|
|
for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
|
||
|
|
if (!FB.test(F))
|
||
|
|
continue;
|
||
|
|
UseHvx = true;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
bool HasHvxVer = false;
|
||
|
|
for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
|
||
|
|
ExtensionHVXV66, ExtensionHVXV67}) {
|
||
|
|
if (!FB.test(F))
|
||
|
|
continue;
|
||
|
|
HasHvxVer = true;
|
||
|
|
UseHvx = true;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!UseHvx || HasHvxVer)
|
||
|
|
return FB;
|
||
|
|
|
||
|
|
// HasHvxVer is false, and UseHvx is true.
|
||
|
|
switch (CpuArch) {
|
||
|
|
case ArchV67:
|
||
|
|
FB.set(ExtensionHVXV67);
|
||
|
|
LLVM_FALLTHROUGH;
|
||
|
|
case ArchV66:
|
||
|
|
FB.set(ExtensionHVXV66);
|
||
|
|
LLVM_FALLTHROUGH;
|
||
|
|
case ArchV65:
|
||
|
|
FB.set(ExtensionHVXV65);
|
||
|
|
LLVM_FALLTHROUGH;
|
||
|
|
case ArchV62:
|
||
|
|
FB.set(ExtensionHVXV62);
|
||
|
|
LLVM_FALLTHROUGH;
|
||
|
|
case ArchV60:
|
||
|
|
FB.set(ExtensionHVXV60);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
return FB;
|
||
|
|
}
|
||
|
|
|
||
|
|
MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
|
||
|
|
StringRef CPU,
|
||
|
|
StringRef FS) {
|
||
|
|
std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
|
||
|
|
StringRef CPUName = Features.first;
|
||
|
|
StringRef ArchFS = Features.second;
|
||
|
|
|
||
|
|
MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(
|
||
|
|
TT, CPUName, /*TuneCPU*/ CPUName, ArchFS);
|
||
|
|
if (X != nullptr && (CPUName == "hexagonv67t"))
|
||
|
|
addArchSubtarget(X, ArchFS);
|
||
|
|
|
||
|
|
if (CPU.equals("help"))
|
||
|
|
exit(0);
|
||
|
|
|
||
|
|
if (!isCPUValid(CPUName.str())) {
|
||
|
|
errs() << "error: invalid CPU \"" << CPUName.str().c_str()
|
||
|
|
<< "\" specified\n";
|
||
|
|
return nullptr;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (HexagonDisableDuplex) {
|
||
|
|
llvm::FeatureBitset Features = X->getFeatureBits();
|
||
|
|
X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
|
||
|
|
}
|
||
|
|
|
||
|
|
X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
|
||
|
|
|
||
|
|
// The Z-buffer instructions are grandfathered in for current
|
||
|
|
// architectures but omitted for new ones. Future instruction
|
||
|
|
// sets may introduce new/conflicting z-buffer instructions.
|
||
|
|
const bool ZRegOnDefault =
|
||
|
|
(CPUName == "hexagonv67") || (CPUName == "hexagonv66");
|
||
|
|
if (ZRegOnDefault) {
|
||
|
|
llvm::FeatureBitset Features = X->getFeatureBits();
|
||
|
|
X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));
|
||
|
|
}
|
||
|
|
|
||
|
|
return X;
|
||
|
|
}
|
||
|
|
|
||
|
|
void Hexagon_MC::addArchSubtarget(MCSubtargetInfo const *STI,
|
||
|
|
StringRef FS) {
|
||
|
|
assert(STI != nullptr);
|
||
|
|
if (STI->getCPU().contains("t")) {
|
||
|
|
auto ArchSTI = createHexagonMCSubtargetInfo(
|
||
|
|
STI->getTargetTriple(),
|
||
|
|
STI->getCPU().substr(0, STI->getCPU().size() - 1), FS);
|
||
|
|
std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
|
||
|
|
ArchSubtarget[std::string(STI->getCPU())] =
|
||
|
|
std::unique_ptr<MCSubtargetInfo const>(ArchSTI);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) {
|
||
|
|
static std::map<StringRef,unsigned> ElfFlags = {
|
||
|
|
{"hexagonv5", ELF::EF_HEXAGON_MACH_V5},
|
||
|
|
{"hexagonv55", ELF::EF_HEXAGON_MACH_V55},
|
||
|
|
{"hexagonv60", ELF::EF_HEXAGON_MACH_V60},
|
||
|
|
{"hexagonv62", ELF::EF_HEXAGON_MACH_V62},
|
||
|
|
{"hexagonv65", ELF::EF_HEXAGON_MACH_V65},
|
||
|
|
{"hexagonv66", ELF::EF_HEXAGON_MACH_V66},
|
||
|
|
{"hexagonv67", ELF::EF_HEXAGON_MACH_V67},
|
||
|
|
{"hexagonv67t", ELF::EF_HEXAGON_MACH_V67T},
|
||
|
|
};
|
||
|
|
|
||
|
|
auto F = ElfFlags.find(STI.getCPU());
|
||
|
|
assert(F != ElfFlags.end() && "Unrecognized Architecture");
|
||
|
|
return F->second;
|
||
|
|
}
|
||
|
|
|
||
|
|
llvm::ArrayRef<MCPhysReg> Hexagon_MC::GetVectRegRev() {
|
||
|
|
return makeArrayRef(VectRegRev);
|
||
|
|
}
|
||
|
|
|
||
|
|
namespace {
|
||
|
|
class HexagonMCInstrAnalysis : public MCInstrAnalysis {
|
||
|
|
public:
|
||
|
|
HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
|
||
|
|
|
||
|
|
bool isUnconditionalBranch(MCInst const &Inst) const override {
|
||
|
|
//assert(!HexagonMCInstrInfo::isBundle(Inst));
|
||
|
|
return MCInstrAnalysis::isUnconditionalBranch(Inst);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool isConditionalBranch(MCInst const &Inst) const override {
|
||
|
|
//assert(!HexagonMCInstrInfo::isBundle(Inst));
|
||
|
|
return MCInstrAnalysis::isConditionalBranch(Inst);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
|
||
|
|
uint64_t Size, uint64_t &Target) const override {
|
||
|
|
if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
|
||
|
|
isConditionalBranch(Inst)))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
//assert(!HexagonMCInstrInfo::isBundle(Inst));
|
||
|
|
if(!HexagonMCInstrInfo::isExtendable(*Info, Inst))
|
||
|
|
return false;
|
||
|
|
auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
|
||
|
|
assert(Extended.isExpr());
|
||
|
|
int64_t Value;
|
||
|
|
if(!Extended.getExpr()->evaluateAsAbsolute(Value))
|
||
|
|
return false;
|
||
|
|
Target = Value;
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
};
|
||
|
|
}
|
||
|
|
|
||
|
|
static MCInstrAnalysis *createHexagonMCInstrAnalysis(const MCInstrInfo *Info) {
|
||
|
|
return new HexagonMCInstrAnalysis(Info);
|
||
|
|
}
|
||
|
|
|
||
|
|
// Force static initialization.
|
||
|
|
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTargetMC() {
|
||
|
|
// Register the MC asm info.
|
||
|
|
RegisterMCAsmInfoFn X(getTheHexagonTarget(), createHexagonMCAsmInfo);
|
||
|
|
|
||
|
|
// Register the MC instruction info.
|
||
|
|
TargetRegistry::RegisterMCInstrInfo(getTheHexagonTarget(),
|
||
|
|
createHexagonMCInstrInfo);
|
||
|
|
|
||
|
|
// Register the MC register info.
|
||
|
|
TargetRegistry::RegisterMCRegInfo(getTheHexagonTarget(),
|
||
|
|
createHexagonMCRegisterInfo);
|
||
|
|
|
||
|
|
// Register the MC subtarget info.
|
||
|
|
TargetRegistry::RegisterMCSubtargetInfo(getTheHexagonTarget(),
|
||
|
|
Hexagon_MC::createHexagonMCSubtargetInfo);
|
||
|
|
|
||
|
|
// Register the MC Code Emitter
|
||
|
|
TargetRegistry::RegisterMCCodeEmitter(getTheHexagonTarget(),
|
||
|
|
createHexagonMCCodeEmitter);
|
||
|
|
|
||
|
|
// Register the asm backend
|
||
|
|
TargetRegistry::RegisterMCAsmBackend(getTheHexagonTarget(),
|
||
|
|
createHexagonAsmBackend);
|
||
|
|
|
||
|
|
|
||
|
|
// Register the MC instruction analyzer.
|
||
|
|
TargetRegistry::RegisterMCInstrAnalysis(getTheHexagonTarget(),
|
||
|
|
createHexagonMCInstrAnalysis);
|
||
|
|
|
||
|
|
// Register the obj streamer
|
||
|
|
TargetRegistry::RegisterELFStreamer(getTheHexagonTarget(),
|
||
|
|
createMCStreamer);
|
||
|
|
|
||
|
|
// Register the obj target streamer
|
||
|
|
TargetRegistry::RegisterObjectTargetStreamer(getTheHexagonTarget(),
|
||
|
|
createHexagonObjectTargetStreamer);
|
||
|
|
|
||
|
|
// Register the asm streamer
|
||
|
|
TargetRegistry::RegisterAsmTargetStreamer(getTheHexagonTarget(),
|
||
|
|
createMCAsmTargetStreamer);
|
||
|
|
|
||
|
|
// Register the MC Inst Printer
|
||
|
|
TargetRegistry::RegisterMCInstPrinter(getTheHexagonTarget(),
|
||
|
|
createHexagonMCInstPrinter);
|
||
|
|
}
|