From e077b08e25179ad886068d524ab5410f2c15e253 Mon Sep 17 00:00:00 2001 From: huatux Date: Fri, 1 Dec 2023 11:33:35 +0800 Subject: [PATCH] update to gcc 11.4.0 musl 1.2.4 binutils 2.41 isl 0.26 --- Makefile | 18 +- hashes/binutils-2.35.2.tar.xz.sha1 | 1 + hashes/binutils-2.41.tar.xz.sha1 | 1 + hashes/config.sub.28ea239c53a2.sha1 | 1 + hashes/gcc-11.3.0.tar.xz.sha1 | 1 + hashes/gcc-11.4.0.tar.xz.sha1 | 1 + hashes/gcc-13.2.0.tar.xz.sha1 | 1 + hashes/gmp-6.3.0.tar.bz2.sha1 | 1 + hashes/isl-0.26.tar.bz2.sha1 | 1 + hashes/linux-4.19.274.tar.xz.sha1 | 1 + hashes/linux-4.20.tar.xz.sha1 | 1 + hashes/mpc-1.3.1.tar.gz.sha1 | 1 + hashes/mpfr-4.2.1.tar.gz.sha1 | 1 + hashes/musl-1.2.4.tar.gz.sha1 | 1 + patches/binutils-2.41/0001-j2.diff | 561 ++++++++++++++++++++ patches/gcc-11.4.0/0001-ssp_nonshared.diff | 14 + patches/gcc-11.4.0/0002-posix_memalign.diff | 30 ++ patches/gcc-11.4.0/0003-j2.diff | 346 ++++++++++++ patches/gcc-11.4.0/0004-static-pie.diff | 92 ++++ patches/gcc-11.4.0/0005-m68k-sqrt.diff | 20 + 20 files changed, 1085 insertions(+), 9 deletions(-) create mode 100644 hashes/binutils-2.35.2.tar.xz.sha1 create mode 100644 hashes/binutils-2.41.tar.xz.sha1 create mode 100644 hashes/config.sub.28ea239c53a2.sha1 create mode 100644 hashes/gcc-11.3.0.tar.xz.sha1 create mode 100644 hashes/gcc-11.4.0.tar.xz.sha1 create mode 100644 hashes/gcc-13.2.0.tar.xz.sha1 create mode 100644 hashes/gmp-6.3.0.tar.bz2.sha1 create mode 100644 hashes/isl-0.26.tar.bz2.sha1 create mode 100644 hashes/linux-4.19.274.tar.xz.sha1 create mode 100644 hashes/linux-4.20.tar.xz.sha1 create mode 100644 hashes/mpc-1.3.1.tar.gz.sha1 create mode 100644 hashes/mpfr-4.2.1.tar.gz.sha1 create mode 100644 hashes/musl-1.2.4.tar.gz.sha1 create mode 100644 patches/binutils-2.41/0001-j2.diff create mode 100644 patches/gcc-11.4.0/0001-ssp_nonshared.diff create mode 100644 patches/gcc-11.4.0/0002-posix_memalign.diff create mode 100644 patches/gcc-11.4.0/0003-j2.diff create mode 100644 patches/gcc-11.4.0/0004-static-pie.diff create mode 100644 patches/gcc-11.4.0/0005-m68k-sqrt.diff diff --git a/Makefile b/Makefile index 09f8c2d..4171976 100644 --- a/Makefile +++ b/Makefile @@ -1,14 +1,14 @@ SOURCES = sources -CONFIG_SUB_REV = 3d5db9ebe860 -BINUTILS_VER = 2.33.1 -GCC_VER = 9.4.0 -MUSL_VER = 1.2.3 -GMP_VER = 6.1.2 -MPC_VER = 1.1.0 -MPFR_VER = 4.0.2 -LINUX_VER = headers-4.19.88-1 +CONFIG_SUB_REV = 28ea239c53a2 +BINUTILS_VER = 2.41 +GCC_VER = 11.4.0 +MUSL_VER = 1.2.4 +GMP_VER = 6.3.0 +MPC_VER = 1.3.1 +MPFR_VER = 4.2.1 +LINUX_VER = 4.19.274 GNU_SITE = https://ftpmirror.gnu.org/gnu GCC_SITE = $(GNU_SITE)/gcc @@ -16,7 +16,7 @@ BINUTILS_SITE = $(GNU_SITE)/binutils GMP_SITE = $(GNU_SITE)/gmp MPC_SITE = $(GNU_SITE)/mpc MPFR_SITE = $(GNU_SITE)/mpfr -ISL_SITE = http://isl.gforge.inria.fr/ +ISL_SITE = https://libisl.sourceforge.io MUSL_SITE = https://musl.libc.org/releases MUSL_REPO = git://git.musl-libc.org/musl diff --git a/hashes/binutils-2.35.2.tar.xz.sha1 b/hashes/binutils-2.35.2.tar.xz.sha1 new file mode 100644 index 0000000..2abe395 --- /dev/null +++ b/hashes/binutils-2.35.2.tar.xz.sha1 @@ -0,0 +1 @@ +2dd8d1ce34dc7b1cb2073123e30c4901221835b0 binutils-2.35.2.tar.xz diff --git a/hashes/binutils-2.41.tar.xz.sha1 b/hashes/binutils-2.41.tar.xz.sha1 new file mode 100644 index 0000000..c5c2522 --- /dev/null +++ b/hashes/binutils-2.41.tar.xz.sha1 @@ -0,0 +1 @@ +0e008260a958bbd10182ee3384672ae0a310eece binutils-2.41.tar.xz diff --git a/hashes/config.sub.28ea239c53a2.sha1 b/hashes/config.sub.28ea239c53a2.sha1 new file mode 100644 index 0000000..86ab3b9 --- /dev/null +++ b/hashes/config.sub.28ea239c53a2.sha1 @@ -0,0 +1 @@ +a5d79f0aaa1c5ce20a0b490f33ae0623e258d2ff config.sub diff --git a/hashes/gcc-11.3.0.tar.xz.sha1 b/hashes/gcc-11.3.0.tar.xz.sha1 new file mode 100644 index 0000000..b767a40 --- /dev/null +++ b/hashes/gcc-11.3.0.tar.xz.sha1 @@ -0,0 +1 @@ +cf86a48278f9a6f4b03d4390550577b20353b4e9 gcc-11.3.0.tar.xz diff --git a/hashes/gcc-11.4.0.tar.xz.sha1 b/hashes/gcc-11.4.0.tar.xz.sha1 new file mode 100644 index 0000000..704439f --- /dev/null +++ b/hashes/gcc-11.4.0.tar.xz.sha1 @@ -0,0 +1 @@ +03f21dce9edf9092e38b4e23dd27b29f6ab56f63 gcc-11.4.0.tar.xz diff --git a/hashes/gcc-13.2.0.tar.xz.sha1 b/hashes/gcc-13.2.0.tar.xz.sha1 new file mode 100644 index 0000000..91f3910 --- /dev/null +++ b/hashes/gcc-13.2.0.tar.xz.sha1 @@ -0,0 +1 @@ +5f95b6d042fb37d45c6cbebfc91decfbc4fb493c gcc-13.2.0.tar.xz diff --git a/hashes/gmp-6.3.0.tar.bz2.sha1 b/hashes/gmp-6.3.0.tar.bz2.sha1 new file mode 100644 index 0000000..b020d0e --- /dev/null +++ b/hashes/gmp-6.3.0.tar.bz2.sha1 @@ -0,0 +1 @@ +32d21c4fae046de45e8fce37bf4002236d283b71 gmp-6.3.0.tar.bz2 diff --git a/hashes/isl-0.26.tar.bz2.sha1 b/hashes/isl-0.26.tar.bz2.sha1 new file mode 100644 index 0000000..5d1f1e6 --- /dev/null +++ b/hashes/isl-0.26.tar.bz2.sha1 @@ -0,0 +1 @@ +7b6c2ed0d14a18214dccfffdcb12f277158e70d9 isl-0.26.tar.bz2 diff --git a/hashes/linux-4.19.274.tar.xz.sha1 b/hashes/linux-4.19.274.tar.xz.sha1 new file mode 100644 index 0000000..d110940 --- /dev/null +++ b/hashes/linux-4.19.274.tar.xz.sha1 @@ -0,0 +1 @@ +865d31c52154c15b8ea946f93bacefea99a01a04 linux-4.19.274.tar.xz diff --git a/hashes/linux-4.20.tar.xz.sha1 b/hashes/linux-4.20.tar.xz.sha1 new file mode 100644 index 0000000..82eec1e --- /dev/null +++ b/hashes/linux-4.20.tar.xz.sha1 @@ -0,0 +1 @@ +f3e78fc0cf8ddd62f7859ac4a54a18a43b43e75a linux-4.20.tar.xz diff --git a/hashes/mpc-1.3.1.tar.gz.sha1 b/hashes/mpc-1.3.1.tar.gz.sha1 new file mode 100644 index 0000000..a2856f8 --- /dev/null +++ b/hashes/mpc-1.3.1.tar.gz.sha1 @@ -0,0 +1 @@ +bac1c1fa79f5602df1e29e4684e103ad55714e02 mpc-1.3.1.tar.gz diff --git a/hashes/mpfr-4.2.1.tar.gz.sha1 b/hashes/mpfr-4.2.1.tar.gz.sha1 new file mode 100644 index 0000000..ca76ea8 --- /dev/null +++ b/hashes/mpfr-4.2.1.tar.gz.sha1 @@ -0,0 +1 @@ +ca7a96560f09b548855f7f97b20cba8106f2f203 mpfr-4.2.1.tar.gz diff --git a/hashes/musl-1.2.4.tar.gz.sha1 b/hashes/musl-1.2.4.tar.gz.sha1 new file mode 100644 index 0000000..0f94407 --- /dev/null +++ b/hashes/musl-1.2.4.tar.gz.sha1 @@ -0,0 +1 @@ +78eb982244b857dbacb2ead25cc0f631ce44204d musl-1.2.4.tar.gz diff --git a/patches/binutils-2.41/0001-j2.diff b/patches/binutils-2.41/0001-j2.diff new file mode 100644 index 0000000..3286a53 --- /dev/null +++ b/patches/binutils-2.41/0001-j2.diff @@ -0,0 +1,561 @@ +diff '--color=auto' -Nur binutils-2.41.orig/bfd/archures.c binutils-2.41/bfd/archures.c +--- binutils-2.41.orig/bfd/archures.c 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/bfd/archures.c 2023-12-01 08:09:33.412615401 +0800 +@@ -288,6 +288,8 @@ + .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + .#define bfd_mach_sh2a_or_sh4 0x2a3 + .#define bfd_mach_sh2a_or_sh3e 0x2a4 ++.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 ++.#define bfd_mach_shj2 0x2c + .#define bfd_mach_sh2e 0x2e + .#define bfd_mach_sh3 0x30 + .#define bfd_mach_sh3_nommu 0x31 +diff '--color=auto' -Nur binutils-2.41.orig/bfd/bfd-in2.h binutils-2.41/bfd/bfd-in2.h +--- binutils-2.41.orig/bfd/bfd-in2.h 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/bfd/bfd-in2.h 2023-12-01 08:10:18.263813888 +0800 +@@ -1541,6 +1541,8 @@ + #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + #define bfd_mach_sh2a_or_sh4 0x2a3 + #define bfd_mach_sh2a_or_sh3e 0x2a4 ++#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 ++#define bfd_mach_shj2 0x2c + #define bfd_mach_sh2e 0x2e + #define bfd_mach_sh3 0x30 + #define bfd_mach_sh3_nommu 0x31 +diff '--color=auto' -Nur binutils-2.41.orig/bfd/cpu-sh.c binutils-2.41/bfd/cpu-sh.c +--- binutils-2.41.orig/bfd/cpu-sh.c 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/bfd/cpu-sh.c 2023-12-01 08:12:28.417488503 +0800 +@@ -63,7 +63,9 @@ + N (bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, "sh2a-nofpu-or-sh4-nommu-nofpu", false, arch_info_struct + 16), + N (bfd_mach_sh2a_nofpu_or_sh3_nommu, "sh2a-nofpu-or-sh3-nommu", false, arch_info_struct + 17), + N (bfd_mach_sh2a_or_sh4, "sh2a-or-sh4", false, arch_info_struct + 18), +- N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", false, NULL) ++ N (bfd_mach_sh2a_or_sh3e, "sh2a-or-sh3e", FALSE, arch_info_struct + 19), ++ N (bfd_mach_shj2, "j2", FALSE, arch_info_struct + 20), ++ N (bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, "sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu", FALSE, NULL) + }; + + const bfd_arch_info_type bfd_sh_arch = +diff '--color=auto' -Nur binutils-2.41.orig/binutils/readelf.c binutils-2.41/binutils/readelf.c +--- binutils-2.41.orig/binutils/readelf.c 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/binutils/readelf.c 2023-12-01 08:13:41.980174526 +0800 +@@ -4164,6 +4164,8 @@ + case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break; + case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break; + case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break; ++ case EF_SHJ2: strcat (buf, ", j2"); break; ++ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break; + default: strcat (buf, _(", unknown ISA")); break; + } + +diff '--color=auto' -Nur binutils-2.41.orig/gas/config/tc-sh.c binutils-2.41/gas/config/tc-sh.c +--- binutils-2.41.orig/gas/config/tc-sh.c 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/config/tc-sh.c 2023-12-01 08:18:15.651287769 +0800 +@@ -1251,6 +1251,8 @@ + ptr++; + } + get_operand (&ptr, operand + 2); ++ if (strcmp (info->name,"cas") == 0) ++ operand[2].type = A_IND_0; + } + else + { +@@ -1790,6 +1792,10 @@ + goto fail; + reg_m = 4; + break; ++ case A_IND_0: ++ if (user->reg != 0) ++ goto fail; ++ break; + + default: + printf (_("unhandled %d\n"), arg); +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.41/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2023-12-01 08:20:29.900881703 +0800 +@@ -12,8 +12,6 @@ + sh2a_nofpu_or_sh3_nommu: + ! Instructions introduced into sh2a-nofpu-or-sh3-nommu + pref @r4 ;!/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + + ! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.41/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2023-12-01 08:23:46.713343578 +0800 +@@ -12,7 +12,7 @@ + sh2a_nofpu_or_sh4_nommu_nofpu: + ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -119,8 +119,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.41/gas/testsuite/gas/sh/arch/sh2a-nofpu.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2023-12-01 08:25:40.991292686 +0800 +@@ -64,7 +64,7 @@ + movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(,), */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -171,8 +171,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.41/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2023-12-01 08:48:46.674506053 +0800 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh2a-or-sh3e + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -124,8 +124,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.41/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2023-12-01 08:51:02.968071046 +0800 +@@ -39,7 +39,7 @@ + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub ,*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc ,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -150,8 +150,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.41/gas/testsuite/gas/sh/arch/sh2a.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh2a.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh2a.s 2023-12-01 08:52:44.038265418 +0800 +@@ -16,7 +16,7 @@ + fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s ,@(,) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} + fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(,), */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -140,8 +140,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.41/gas/testsuite/gas/sh/arch/sh3-dsp.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh3-dsp.s 2023-12-01 08:58:28.924021531 +0800 +@@ -12,7 +12,7 @@ + sh3_dsp: + ! Instructions introduced into sh3-dsp + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -152,8 +152,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.41/gas/testsuite/gas/sh/arch/sh3-nommu.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh3-nommu.s 2023-12-01 09:04:06.433934192 +0800 +@@ -26,7 +26,7 @@ + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@- */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@- */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -133,8 +133,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.41/gas/testsuite/gas/sh/arch/sh3.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh3.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh3.s 2023-12-01 09:06:11.683681469 +0800 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh3 + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -128,8 +128,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.41/gas/testsuite/gas/sh/arch/sh3e.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh3e.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh3e.s 2023-12-01 09:00:25.657912653 +0800 +@@ -12,7 +12,7 @@ + sh3e: + ! Instructions introduced into sh3e + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -132,8 +132,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.41/gas/testsuite/gas/sh/arch/sh4-nofpu.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2023-12-01 09:12:21.949033480 +0800 +@@ -12,7 +12,7 @@ + sh4_nofpu: + ! Instructions introduced into sh4-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -136,8 +136,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.41/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2023-12-01 09:13:36.291700116 +0800 +@@ -24,7 +24,7 @@ + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@- */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@- */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -139,8 +139,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.41/gas/testsuite/gas/sh/arch/sh4.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh4.s 2023-12-01 09:14:45.822453361 +0800 +@@ -17,7 +17,7 @@ + fsrra fr1 ;!/* 1111nnnn01111101 fsrra */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} + ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -145,8 +145,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.41/gas/testsuite/gas/sh/arch/sh4a-nofpu.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2023-12-01 09:09:25.512199607 +0800 +@@ -19,7 +19,7 @@ + prefi @r4 ;!/* 0000nnnn11010011 prefi @ */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -143,8 +143,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.41/gas/testsuite/gas/sh/arch/sh4a.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4a.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh4a.s 2023-12-01 09:11:04.226427874 +0800 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh4a + fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -147,8 +147,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.41/gas/testsuite/gas/sh/arch/sh4al-dsp.s +--- binutils-2.41.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2023-12-01 09:08:05.129643022 +0800 +@@ -48,7 +48,7 @@ + dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap , */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} + dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap , */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -202,8 +202,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff '--color=auto' -Nur binutils-2.41.orig/include/elf/sh.h binutils-2.41/include/elf/sh.h +--- binutils-2.41.orig/include/elf/sh.h 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/include/elf/sh.h 2023-12-01 09:18:07.422839802 +0800 +@@ -39,6 +39,7 @@ + #define EF_SH2E 11 + #define EF_SH4A 12 + #define EF_SH2A 13 ++#define EF_SHJ2 14 + + #define EF_SH4_NOFPU 16 + #define EF_SH4A_NOFPU 17 +@@ -50,6 +51,7 @@ + #define EF_SH2A_SH3_NOFPU 22 + #define EF_SH2A_SH4 23 + #define EF_SH2A_SH3E 24 ++#define EF_SH2A_SH3_SHJ2 25 + + /* This one can only mix in objects from other EF_SH5 objects. */ + #define EF_SH5 10 +@@ -72,7 +74,8 @@ + /* EF_SH2E */ bfd_mach_sh2e , \ + /* EF_SH4A */ bfd_mach_sh4a , \ + /* EF_SH2A */ bfd_mach_sh2a , \ +-/* 14, 15 */ 0, 0, \ ++/* EF_SHJ2 */ bfd_mach_shj2 , \ ++/* 15 */ 0, \ + /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ + /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ + /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ +@@ -81,7 +84,8 @@ + /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ + /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ + /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ +-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e ++/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \ ++/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu + + /* Convert arch_sh* into EF_SH*. */ + int sh_find_elf_flags (unsigned int arch_set); +diff '--color=auto' -Nur binutils-2.41.orig/opcodes/sh-dis.c binutils-2.41/opcodes/sh-dis.c +--- binutils-2.41.orig/opcodes/sh-dis.c 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/opcodes/sh-dis.c 2023-12-01 09:19:03.401836696 +0800 +@@ -866,6 +866,9 @@ + case XMTRX_M4: + fprintf_fn (stream, "xmtrx"); + break; ++ case A_IND_0: ++ fprintf_fn (stream, "@r0"); ++ break; + default: + abort (); + } +diff '--color=auto' -Nur binutils-2.41.orig/opcodes/sh-opc.h binutils-2.41/opcodes/sh-opc.h +--- binutils-2.41.orig/opcodes/sh-opc.h 2023-07-03 07:00:00.000000000 +0800 ++++ binutils-2.41/opcodes/sh-opc.h 2023-12-01 09:28:20.419854381 +0800 +@@ -192,7 +192,8 @@ + FPUL_N, + FPUL_M, + FPSCR_N, +- FPSCR_M ++ FPSCR_M, ++ A_IND_0 + } + sh_arg_type; + +@@ -216,9 +217,11 @@ + #define arch_sh4_base (1 << 5) + #define arch_sh4a_base (1 << 6) + #define arch_sh2a_base (1 << 7) +-#define arch_sh_base_mask MASK (0, 7) ++#define arch_shj2_base (1 << 8) ++#define arch_sh2a_sh3_shj2_base (1 << 9) ++#define arch_sh_base_mask MASK (0, 9) + +-/* Bits 8 ... 24 are currently free. */ ++/* Bits 10 ... 24 are currently free. */ + + /* This is an annotation on instruction types, but we + abuse the arch field in instructions to denote it. */ +@@ -256,6 +259,8 @@ + #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) + #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) + #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) ++#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co) + + #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) + #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) +@@ -320,7 +325,8 @@ + #define arch_sh2_up (arch_sh2 \ + | arch_sh2e_up \ + | arch_sh2a_nofpu_or_sh3_nommu_up \ +- | arch_sh_dsp_up) ++ | arch_sh_dsp_up \ ++ | arch_shj2_up) + #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ + | arch_sh2a_or_sh3e_up \ +@@ -346,6 +352,12 @@ + #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ + | arch_sh4a_up \ + | arch_sh4al_dsp_up) ++#define arch_shj2_up ( arch_shj2) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \ ++ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ ++ | arch_sh2a_or_sh3e_up \ ++ | arch_sh3_nommu_up \ ++ | arch_shj2_up) + + /* Right branches. */ + #define arch_sh2e_up (arch_sh2e \ +@@ -714,9 +726,9 @@ + + /* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8S,HEX_8}, arch_sh_dsp_up}, + +-/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + +-/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + + /* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, + +@@ -1194,6 +1206,7 @@ + {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ + {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, ++/* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up}, + + { 0, {0}, {0}, 0 } + }; diff --git a/patches/gcc-11.4.0/0001-ssp_nonshared.diff b/patches/gcc-11.4.0/0001-ssp_nonshared.diff new file mode 100644 index 0000000..0b991d9 --- /dev/null +++ b/patches/gcc-11.4.0/0001-ssp_nonshared.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 7837553958b..3c81c5798d8 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -980,7 +980,8 @@ proper position among the other output files. */ + #ifndef LINK_SSP_SPEC + #ifdef TARGET_LIBC_PROVIDES_SSP + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ +- "|fstack-protector-strong|fstack-protector-explicit:}" ++ "|fstack-protector-strong|fstack-protector-explicit" \ ++ ":-lssp_nonshared}" + #else + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ + "|fstack-protector-strong|fstack-protector-explicit" \ diff --git a/patches/gcc-11.4.0/0002-posix_memalign.diff b/patches/gcc-11.4.0/0002-posix_memalign.diff new file mode 100644 index 0000000..1d80096 --- /dev/null +++ b/patches/gcc-11.4.0/0002-posix_memalign.diff @@ -0,0 +1,30 @@ +diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h +index 1b0bfe37852..d7b2b19bb3c 100644 +--- a/gcc/config/i386/pmm_malloc.h ++++ b/gcc/config/i386/pmm_malloc.h +@@ -27,12 +27,13 @@ + #include + + /* We can't depend on since the prototype of posix_memalign +- may not be visible. */ ++ may not be visible and we can't pollute the namespace either. */ + #ifndef __cplusplus +-extern int posix_memalign (void **, size_t, size_t); ++extern int _mm_posix_memalign (void **, size_t, size_t) + #else +-extern "C" int posix_memalign (void **, size_t, size_t) throw (); ++extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw () + #endif ++__asm__("posix_memalign"); + + static __inline void * + _mm_malloc (size_t __size, size_t __alignment) +@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment) + return malloc (__size); + if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4)) + __alignment = sizeof (void *); +- if (posix_memalign (&__ptr, __alignment, __size) == 0) ++ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0) + return __ptr; + else + return NULL; diff --git a/patches/gcc-11.4.0/0003-j2.diff b/patches/gcc-11.4.0/0003-j2.diff new file mode 100644 index 0000000..245b910 --- /dev/null +++ b/patches/gcc-11.4.0/0003-j2.diff @@ -0,0 +1,346 @@ +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 357b0bed067..528add999f2 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -556,7 +556,7 @@ s390*-*-*) + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -3202,18 +3202,18 @@ s390x-ibm-tpf*) + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh*-*-linux* | \ + sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -3280,6 +3280,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -3301,7 +3302,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -3310,9 +3311,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + case ${target} in + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -3327,7 +3328,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + m1 | m2 | m2e | m3 | m3e | \ + m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ +- m2a | m2a-single | m2a-single-only | m2a-nofpu) ++ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -3344,7 +3346,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -5175,6 +5177,8 @@ case "${target}" in + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -5385,7 +5389,7 @@ case ${target} in + tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; +diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c +index 1564109c942..798c1c1c1a3 100644 +--- a/gcc/config/sh/sh.c ++++ b/gcc/config/sh/sh.c +@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str) + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str) + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -771,6 +773,9 @@ got_mode_name:; + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -827,6 +832,8 @@ sh_option_override (void) + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h +index d2280e2ffe6..3a54a896721 100644 +--- a/gcc/config/sh/sh.h ++++ b/gcc/config/sh/sh.h +@@ -85,6 +85,7 @@ extern int code_for_indirect_jump_scratch; + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) +@@ -117,6 +118,7 @@ extern int code_for_indirect_jump_scratch; + #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) + #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) + #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -124,6 +126,7 @@ extern int code_for_indirect_jump_scratch; + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -156,7 +159,7 @@ extern int code_for_indirect_jump_scratch; + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -231,7 +234,8 @@ extern int code_for_indirect_jump_scratch; + %{m2a-single:--isa=sh2a} \ + %{m2a-single-only:--isa=sh2a} \ + %{m2a-nofpu:--isa=sh2a-nofpu} \ +-%{m4al:-dsp}" ++%{m4al:-dsp} \ ++%{mj2:-isa=j2}" + + #define ASM_SPEC SH_ASM_SPEC + +@@ -347,6 +351,7 @@ struct sh_atomic_model + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -390,6 +395,9 @@ extern const sh_atomic_model& selected_atomic_model (void); + #define TARGET_ATOMIC_SOFT_IMASK \ + (selected_atomic_model ().type == sh_atomic_model::soft_imask) + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #endif // __cplusplus + + #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 +@@ -1484,7 +1492,7 @@ extern bool current_function_interrupt; + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -1747,6 +1755,7 @@ enum processor_type { + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt +index b4755a812f3..0989a1c18da 100644 +--- a/gcc/config/sh/sh.opt ++++ b/gcc/config/sh/sh.opt +@@ -65,6 +65,10 @@ m2e + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md +index 2b43f8edb86..118fc5d06db 100644 +--- a/gcc/config/sh/sync.md ++++ b/gcc/config/sh/sync.md +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh +index 888f8ff7f25..29fd6ae45fd 100644 +--- a/gcc/config/sh/t-sh ++++ b/gcc/config/sh/t-sh +@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \ + m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \ + m2a-single,m2a-single-only \ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ +- m4,m4-100,m4-200,m4-300,m4a; do \ ++ m4,m4-100,m4-200,m4-300,m4a \ ++ mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \ + m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \ + m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \ + m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \ +- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al ++ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \ ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true diff --git a/patches/gcc-11.4.0/0004-static-pie.diff b/patches/gcc-11.4.0/0004-static-pie.diff new file mode 100644 index 0000000..232dc5d --- /dev/null +++ b/patches/gcc-11.4.0/0004-static-pie.diff @@ -0,0 +1,92 @@ +diff --git a/gcc/common.opt b/gcc/common.opt +index a75b44ee47e..7c564818b49 100644 +--- a/gcc/common.opt ++++ b/gcc/common.opt +@@ -3473,11 +3473,11 @@ Driver + + no-pie + Driver RejectNegative Negative(shared) +-Don't create a dynamically linked position independent executable. ++Don't create a position independent executable. + + pie + Driver RejectNegative Negative(no-pie) +-Create a dynamically linked position independent executable. ++Create a position independent executable. + + static-pie + Driver RejectNegative Negative(pie) +diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h +index 5ebbf42a13d..bb907d8e89a 100644 +--- a/gcc/config/gnu-user.h ++++ b/gcc/config/gnu-user.h +@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define GNU_USER_TARGET_STARTFILE_SPEC \ + "%{shared:; \ + pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \ +- static:crt1.o%s; \ +- static-pie:rcrt1.o%s; \ ++ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \ + " PIE_SPEC ":Scrt1.o%s; \ + :crt1.o%s} " \ + GNU_USER_TARGET_CRTI " \ +- %{static:crtbeginT.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \ ++ %{shared|" PIE_SPEC ":crtbeginS.o%s; \ ++ static:crtbeginT.o%s; \ + :crtbegin.o%s} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ +@@ -73,11 +72,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + GNU userspace "finalizer" file, `crtn.o'. */ + + #define GNU_USER_TARGET_ENDFILE_SPEC \ +- "%{!static:%{fvtable-verify=none:%s; \ ++ "%{static|static-pie:; \ ++ fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end_preinit.o%s; \ +- fvtable-verify=std:vtv_end.o%s}} \ +- %{static:crtend.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \ ++ fvtable-verify=std:vtv_end.o%s} \ ++ %{shared|" PIE_SPEC ":crtendS.o%s; \ + :crtend.o%s} " \ + GNU_USER_TARGET_CRTN " " \ + CRTOFFLOADEND +@@ -106,7 +105,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define LIB_SPEC GNU_USER_TARGET_LIB_SPEC + + #if defined(HAVE_LD_EH_FRAME_HDR) +-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} " ++#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} " + #endif + + #define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 3c81c5798d8..cd96eac5d12 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -1010,7 +1010,7 @@ proper position among the other output files. */ + #define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC + #define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;" + #else +-#define PIE_SPEC "pie" ++#define PIE_SPEC "pie|static-pie" + #define FPIE1_SPEC "fpie" + #define NO_FPIE1_SPEC FPIE1_SPEC ":;" + #define FPIE2_SPEC "fPIE" +@@ -1034,12 +1034,12 @@ proper position among the other output files. */ + #ifndef LINK_PIE_SPEC + #ifdef HAVE_LD_PIE + #ifndef LD_PIE_SPEC +-#define LD_PIE_SPEC "-pie" ++#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}" + #endif + #else + #define LD_PIE_SPEC "" + #endif +-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " ++#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " + #endif + + #ifndef LINK_BUILDID_SPEC diff --git a/patches/gcc-11.4.0/0005-m68k-sqrt.diff b/patches/gcc-11.4.0/0005-m68k-sqrt.diff new file mode 100644 index 0000000..652efb1 --- /dev/null +++ b/patches/gcc-11.4.0/0005-m68k-sqrt.diff @@ -0,0 +1,20 @@ +diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md +index 59a456cd496..dbfddea41bd 100644 +--- a/gcc/config/m68k/m68k.md ++++ b/gcc/config/m68k/m68k.md +@@ -4174,13 +4174,13 @@ + (define_expand "sqrt2" + [(set (match_operand:FP 0 "nonimmediate_operand" "") + (sqrt:FP (match_operand:FP 1 "general_operand" "")))] +- "TARGET_HARD_FLOAT" ++ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU" + "") + + (define_insn "sqrt2_68881" + [(set (match_operand:FP 0 "nonimmediate_operand" "=f") + (sqrt:FP (match_operand:FP 1 "general_operand" "fm")))] +- "TARGET_68881" ++ "TARGET_68881 && TARGET_68040" + { + if (FP_REG_P (operands[1])) + return "fsqrt%.x %1,%0";