From 3d26f0cf0210150c59b3145b431bce48a04a8c3d Mon Sep 17 00:00:00 2001 From: Rich Felker Date: Wed, 22 Jan 2020 00:02:12 -0500 Subject: [PATCH] add binutils 2.33.1 included are new or1k support patches that are not easily backported to earlier versions. --- hashes/binutils-2.33.1.tar.xz.sha1 | 1 + patches/binutils-2.33.1/0001-j2.diff | 620 +++ .../0002-or1k-32bithost-1.diff | 249 + .../0003-or1k-32bithost-2.diff | 4308 +++++++++++++++++ 4 files changed, 5178 insertions(+) create mode 100644 hashes/binutils-2.33.1.tar.xz.sha1 create mode 100644 patches/binutils-2.33.1/0001-j2.diff create mode 100644 patches/binutils-2.33.1/0002-or1k-32bithost-1.diff create mode 100644 patches/binutils-2.33.1/0003-or1k-32bithost-2.diff diff --git a/hashes/binutils-2.33.1.tar.xz.sha1 b/hashes/binutils-2.33.1.tar.xz.sha1 new file mode 100644 index 0000000..19e5b06 --- /dev/null +++ b/hashes/binutils-2.33.1.tar.xz.sha1 @@ -0,0 +1 @@ +06598868f5fa8efc98427dcb790d42c664f1a1a4 binutils-2.33.1.tar.xz diff --git a/patches/binutils-2.33.1/0001-j2.diff b/patches/binutils-2.33.1/0001-j2.diff new file mode 100644 index 0000000..f08140e --- /dev/null +++ b/patches/binutils-2.33.1/0001-j2.diff @@ -0,0 +1,620 @@ +diff -ur binutils-2.32.orig/bfd/archures.c binutils-2.32/bfd/archures.c +--- binutils-2.32.orig/bfd/archures.c 2019-01-19 11:01:32.000000000 -0500 ++++ binutils-2.32/bfd/archures.c 2019-05-26 15:09:15.968501965 -0400 +@@ -298,6 +298,8 @@ + .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + .#define bfd_mach_sh2a_or_sh4 0x2a3 + .#define bfd_mach_sh2a_or_sh3e 0x2a4 ++.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 ++.#define bfd_mach_shj2 0x2c + .#define bfd_mach_sh2e 0x2e + .#define bfd_mach_sh3 0x30 + .#define bfd_mach_sh3_nommu 0x31 +Only in binutils-2.32/bfd: archures.c.orig +Only in binutils-2.32/bfd: archures.c.rej +diff -ur binutils-2.32.orig/bfd/bfd-in2.h binutils-2.32/bfd/bfd-in2.h +--- binutils-2.32.orig/bfd/bfd-in2.h 2019-01-19 11:01:32.000000000 -0500 ++++ binutils-2.32/bfd/bfd-in2.h 2019-05-26 15:10:21.005775819 -0400 +@@ -2197,6 +2197,8 @@ + #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + #define bfd_mach_sh2a_or_sh4 0x2a3 + #define bfd_mach_sh2a_or_sh3e 0x2a4 ++#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 ++#define bfd_mach_shj2 0x2c + #define bfd_mach_sh2e 0x2e + #define bfd_mach_sh3 0x30 + #define bfd_mach_sh3_nommu 0x31 +Only in binutils-2.32/bfd: bfd-in2.h.orig +Only in binutils-2.32/bfd: bfd-in2.h.rej +diff -ur binutils-2.32.orig/bfd/cpu-sh.c binutils-2.32/bfd/cpu-sh.c +--- binutils-2.32.orig/bfd/cpu-sh.c 2019-01-19 11:01:32.000000000 -0500 ++++ binutils-2.32/bfd/cpu-sh.c 2019-05-26 15:13:00.461455381 -0400 +@@ -43,7 +43,10 @@ + #define SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT arch_info_struct + 16 + #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17 + #define SH2A_OR_SH4_NEXT arch_info_struct + 18 +-#define SH2A_OR_SH3E_NEXT NULL ++#define SH2A_OR_SH3E_NEXT arch_info_struct + 19 ++#define SHJ2_NEXT arch_info_struct + 20 ++#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL ++ + + static const bfd_arch_info_type arch_info_struct[] = + { +@@ -332,6 +335,36 @@ + bfd_arch_default_fill, + SH2A_OR_SH3E_NEXT + }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_shj2, ++ "sh", /* Architecture name. . */ ++ "j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SHJ2_NEXT ++ }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, ++ "sh", /* Architecture name. . */ ++ "sh2a-or-sh3e-or-j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT ++ }, + }; + + const bfd_arch_info_type bfd_sh_arch = +@@ -382,6 +415,8 @@ + { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up }, + { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up }, + { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up }, ++ { bfd_mach_shj2, arch_shj2, arch_shj2_up }, ++ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up }, + { 0, 0, 0 } /* Terminator. */ + }; + +Only in binutils-2.32/bfd: cpu-sh.c.orig +Only in binutils-2.32/bfd: cpu-sh.c.rej +diff -ur binutils-2.32.orig/binutils/readelf.c binutils-2.32/binutils/readelf.c +--- binutils-2.32.orig/binutils/readelf.c 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/binutils/readelf.c 2019-05-26 15:07:03.563950564 -0400 +@@ -3528,6 +3528,8 @@ + case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break; + case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break; + case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break; ++ case EF_SHJ2: strcat (buf, ", j2"); break; ++ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break; + default: strcat (buf, _(", unknown ISA")); break; + } + +Only in binutils-2.32/binutils: readelf.c.orig +diff -ur binutils-2.32.orig/gas/config/tc-sh.c binutils-2.32/gas/config/tc-sh.c +--- binutils-2.32.orig/gas/config/tc-sh.c 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/config/tc-sh.c 2019-05-26 15:07:03.567950581 -0400 +@@ -1251,6 +1251,8 @@ + ptr++; + } + get_operand (&ptr, operand + 2); ++ if (strcmp (info->name,"cas") == 0) ++ operand[2].type = A_IND_0; + } + else + { +@@ -1790,7 +1792,10 @@ + goto fail; + reg_m = 4; + break; +- ++ case A_IND_0: ++ if (user->reg != 0) ++ goto fail; ++ break; + default: + printf (_("unhandled %d\n"), arg); + goto fail; +Only in binutils-2.32/gas/config: tc-sh.c.orig +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-05-26 15:07:03.568950585 -0400 +@@ -12,8 +12,6 @@ + sh2a_nofpu_or_sh3_nommu: + ! Instructions introduced into sh2a-nofpu-or-sh3-nommu + pref @r4 ;!/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + + ! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-05-26 15:07:03.570950593 -0400 +@@ -12,7 +12,7 @@ + sh2a_nofpu_or_sh4_nommu_nofpu: + ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -119,8 +119,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-05-26 15:07:03.571950597 -0400 +@@ -64,7 +64,7 @@ + movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(,), */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -171,8 +171,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-05-26 15:07:03.572950601 -0400 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh2a-or-sh3e + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -124,8 +124,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-05-26 15:07:03.574950610 -0400 +@@ -39,7 +39,7 @@ + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub ,*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc ,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -150,8 +150,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s 2019-05-26 15:07:03.575950614 -0400 +@@ -16,7 +16,7 @@ + fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s ,@(,) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} + fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(,), */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -140,8 +140,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-05-26 15:07:03.577950622 -0400 +@@ -12,7 +12,7 @@ + sh3_dsp: + ! Instructions introduced into sh3-dsp + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -152,8 +152,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-05-26 15:07:03.578950626 -0400 +@@ -26,7 +26,7 @@ + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@- */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@- */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -133,8 +133,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s 2019-05-26 15:07:03.579950630 -0400 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh3 + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -128,8 +128,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s 2019-05-26 15:07:03.581950639 -0400 +@@ -12,7 +12,7 @@ + sh3e: + ! Instructions introduced into sh3e + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -132,8 +132,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-05-26 15:07:03.582950643 -0400 +@@ -12,7 +12,7 @@ + sh4_nofpu: + ! Instructions introduced into sh4-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -136,8 +136,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-05-26 15:07:03.583950647 -0400 +@@ -24,7 +24,7 @@ + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@- */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@- */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -139,8 +139,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s 2019-05-26 15:07:03.585950655 -0400 +@@ -17,7 +17,7 @@ + fsrra fr1 ;!/* 1111nnnn01111101 fsrra */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} + ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -145,8 +145,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-05-26 15:07:03.586950659 -0400 +@@ -19,7 +19,7 @@ + prefi @r4 ;!/* 0000nnnn11010011 prefi @ */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -143,8 +143,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s 2019-05-26 15:07:03.588950668 -0400 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh4a + fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -147,8 +147,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-05-26 15:07:03.589950672 -0400 +@@ -48,7 +48,7 @@ + dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap , */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} + dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap , */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -202,8 +202,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/include/elf/sh.h binutils-2.32/include/elf/sh.h +--- binutils-2.32.orig/include/elf/sh.h 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/include/elf/sh.h 2019-05-26 15:07:03.590950676 -0400 +@@ -39,6 +39,7 @@ + #define EF_SH2E 11 + #define EF_SH4A 12 + #define EF_SH2A 13 ++#define EF_SHJ2 14 + + #define EF_SH4_NOFPU 16 + #define EF_SH4A_NOFPU 17 +@@ -50,6 +51,7 @@ + #define EF_SH2A_SH3_NOFPU 22 + #define EF_SH2A_SH4 23 + #define EF_SH2A_SH3E 24 ++#define EF_SH2A_SH3_SHJ2 25 + + /* This one can only mix in objects from other EF_SH5 objects. */ + #define EF_SH5 10 +@@ -72,7 +74,8 @@ + /* EF_SH2E */ bfd_mach_sh2e , \ + /* EF_SH4A */ bfd_mach_sh4a , \ + /* EF_SH2A */ bfd_mach_sh2a , \ +-/* 14, 15 */ 0, 0, \ ++/* EF_SHJ2 */ bfd_mach_shj2 , \ ++/* 15 */ 0, \ + /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ + /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ + /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ +@@ -81,7 +84,8 @@ + /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ + /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ + /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ +-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e ++/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \ ++/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu + + /* Convert arch_sh* into EF_SH*. */ + int sh_find_elf_flags (unsigned int arch_set); +diff -ur binutils-2.32.orig/opcodes/sh-dis.c binutils-2.32/opcodes/sh-dis.c +--- binutils-2.32.orig/opcodes/sh-dis.c 2019-01-19 11:01:34.000000000 -0500 ++++ binutils-2.32/opcodes/sh-dis.c 2019-05-26 15:07:03.593950688 -0400 +@@ -856,6 +856,9 @@ + case XMTRX_M4: + fprintf_fn (stream, "xmtrx"); + break; ++ case A_IND_0: ++ fprintf_fn (stream, "@r0"); ++ break; + default: + abort (); + } +Only in binutils-2.32/opcodes: sh-dis.c.orig +diff -ur binutils-2.32.orig/opcodes/sh-opc.h binutils-2.32/opcodes/sh-opc.h +--- binutils-2.32.orig/opcodes/sh-opc.h 2019-01-19 11:01:34.000000000 -0500 ++++ binutils-2.32/opcodes/sh-opc.h 2019-05-26 15:07:03.597950705 -0400 +@@ -191,7 +191,8 @@ + FPUL_N, + FPUL_M, + FPSCR_N, +- FPSCR_M ++ FPSCR_M, ++ A_IND_0 + } + sh_arg_type; + +@@ -215,9 +216,11 @@ + #define arch_sh4_base (1 << 5) + #define arch_sh4a_base (1 << 6) + #define arch_sh2a_base (1 << 7) +-#define arch_sh_base_mask MASK (0, 7) ++#define arch_shj2_base (1 << 8) ++#define arch_sh2a_sh3_shj2_base (1 << 9) ++#define arch_sh_base_mask MASK (0, 9) + +-/* Bits 8 ... 24 are currently free. */ ++/* Bits 10 ... 24 are currently free. */ + + /* This is an annotation on instruction types, but we + abuse the arch field in instructions to denote it. */ +@@ -255,6 +258,8 @@ + #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) + #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) + #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) ++#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co) + + #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) + #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) +@@ -319,7 +324,8 @@ + #define arch_sh2_up (arch_sh2 \ + | arch_sh2e_up \ + | arch_sh2a_nofpu_or_sh3_nommu_up \ +- | arch_sh_dsp_up) ++ | arch_sh_dsp_up \ ++ | arch_shj2_up) + #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ + | arch_sh2a_or_sh3e_up \ +@@ -345,6 +351,12 @@ + #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ + | arch_sh4a_up \ + | arch_sh4al_dsp_up) ++#define arch_shj2_up ( arch_shj2) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \ ++ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ ++ | arch_sh2a_or_sh3e_up \ ++ | arch_sh3_nommu_up \ ++ | arch_shj2_up) + + /* Right branches. */ + #define arch_sh2e_up (arch_sh2e \ +@@ -713,9 +725,9 @@ + + /* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, + +-/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + +-/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + + /* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, + +@@ -1193,7 +1205,7 @@ + {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ + {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, +- ++ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up}, + { 0, {0}, {0}, 0 } + }; + +Only in binutils-2.32/opcodes: sh-opc.h.orig diff --git a/patches/binutils-2.33.1/0002-or1k-32bithost-1.diff b/patches/binutils-2.33.1/0002-or1k-32bithost-1.diff new file mode 100644 index 0000000..90cc09d --- /dev/null +++ b/patches/binutils-2.33.1/0002-or1k-32bithost-1.diff @@ -0,0 +1,249 @@ +From: Stafford Horne +To: GNU Binutils +Cc: Openrisc , dalias@libc.org, Stafford Horne +Subject: [PATCH 1/2] or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts +Date: Wed, 11 Dec 2019 06:49:05 +0900 + +Reported by Rich Felker when building on 32-bit hosts. Backwards jump +negative offsets were not calculated correctly due to improper 32-bit +to 64-bit zero-extension. The 64-bit fields are present because we +are mixing 32-bit and 64-bit architectures in our cpu descriptions. + +Removing 64-bit fixes the issue. We don't use 64-bit, there is an architecture +spec for 64-bit but no implementations or simulators. My thought is if +we need them in the future we should do the proper work to support both +32-bit and 64-bit implementations co-existing then. + +cpu/ChangeLog: + +yyyy-mm-dd Stafford Horne + + PR 25184 + * or1k.cpu (arch or1k): Remove or64 and or64nd machs. + (ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros. + (cpu or1k64bf, mach or64, mach or64nd): Remove definitions. + * or1kcommon.cpu (h-fdr): Remove hardware. + * or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions. + (float-regreg-insn): Remove lf- mnemonic -d instruction pattern. + (float-setflag-insn-base): Remove lf-sf mnemonic -d pattern. + (float-cust-insn): Remove "lf-cust" cust-num "-d" pattern. + (lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove. +--- + cpu/or1k.cpu | 35 +++---------------------- + cpu/or1kcommon.cpu | 14 ---------- + cpu/or1korfpx.cpu | 64 ---------------------------------------------- + 3 files changed, 3 insertions(+), 110 deletions(-) + +diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu +index b796862d1b..9784f7a0fa 100644 +--- a/cpu/or1k.cpu ++++ b/cpu/or1k.cpu +@@ -31,7 +31,7 @@ + (comment "OpenRISC 1000") + (default-alignment aligned) + (insn-lsb0? #t) +- (machs or32 or32nd or64 or64nd) ++ (machs or32 or32nd) + (isas openrisc) + ) + +@@ -44,10 +44,8 @@ + ) + + (define-pmacro OR32-MACHS or32,or32nd) +-(define-pmacro OR64-MACHS or64,or64nd) +-(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd) +-(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd) +-(define-pmacro ORFPX64-MACHS or64,or64nd) ++(define-pmacro ORBIS-MACHS or32,or32nd) ++(define-pmacro ORFPX32-MACHS or32,or32nd) + (define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs + + (define-attr +@@ -100,33 +98,6 @@ + ) + ) + +-(if (keep-mach? (or64 or64nd)) +- (begin +- (define-cpu +- (name or1k64bf) +- (comment "OpenRISC 1000 64-bit CPU family") +- (insn-endian big) +- (data-endian big) +- (word-bitsize 64) +- (file-transform "64") +- ) +- +- (define-mach +- (name or64) +- (comment "Generic OpenRISC 1000 64-bit CPU") +- (cpu or1k64bf) +- (bfd-name "or1k64") +- ) +- +- (define-mach +- (name or64nd) +- (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot") +- (cpu or1k64bf) +- (bfd-name "or1k64nd") +- ) +- ) +- ) +- + (include "or1kcommon.cpu") + (include "or1korbis.cpu") + (include "or1korfpx.cpu") +diff --git a/cpu/or1kcommon.cpu b/cpu/or1kcommon.cpu +index 65154407df..9f102c93a1 100644 +--- a/cpu/or1kcommon.cpu ++++ b/cpu/or1kcommon.cpu +@@ -114,20 +114,6 @@ + (set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0)))) + ) + +-; +-; Hardware: virtual registerts for FPU (double precision) +-; mapped to GPRs +-; +-(define-hardware +- (name h-fdr) +- (comment "or64 floating point registers (double, virtual)") +- (attrs VIRTUAL (MACH ORFPX64-MACHS)) +- (type register DF (32)) +- (indices keyword "" REG-INDICES) +- (get (index) (subword DF (trunc DI (reg h-gpr index)) 0)) +- (set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0)))) +- ) +- + ; + ; Register pairs are offset by 2 for registers r16 and above. This is to + ; be able to allow registers to be call saved in GCC across function calls. +diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu +index f43522f2e6..0bd469cff5 100644 +--- a/cpu/or1korfpx.cpu ++++ b/cpu/or1korfpx.cpu +@@ -84,10 +84,6 @@ + (dnop rASF "source register A (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r2) + (dnop rBSF "source register B (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r3) + +-(dnop rDDF "or64 destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1) +-(dnop rADF "or64 source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r2) +-(dnop rBDF "or64 source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r3) +- + (define-pmacro (double-field-and-ops mnemonic reg offbit op-comment) + (begin + (define-multi-ifield +@@ -152,14 +148,6 @@ + (set SF rDSF (mnemonic SF rASF rBSF)) + () + ) +- (dni (.sym lf- mnemonic -d) +- (.str "lf." mnemonic ".d reg/reg/reg") +- ((MACH ORFPX64-MACHS)) +- (.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF") +- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D)) +- (set DF rDDF (mnemonic DF rADF rBDF)) +- () +- ) + (dni (.sym lf- mnemonic -d32) + (.str "lf." mnemonic ".d regpair/regpair/regpair") + ((MACH ORFPX64A32-MACHS)) +@@ -185,15 +173,6 @@ + () + ) + +-(dni lf-rem-d +- "lf.rem.d reg/reg/reg" +- ((MACH ORFPX64-MACHS)) +- "lf.rem.d $rDDF,$rADF,$rBDF" +- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D) +- (set DF rDDF (rem DF rADF rBDF)) +- () +- ) +- + (dni lf-rem-d32 + "lf.rem.d regpair/regpair/regpair" + ((MACH ORFPX64A32-MACHS)) +@@ -221,15 +200,6 @@ + () + ) + +-(dni lf-itof-d +- "lf.itof.d reg/reg" +- ((MACH ORFPX64-MACHS)) +- "lf.itof.d $rDDF,$rA" +- (+ OPC_FLOAT rDDF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D) +- (set DF rDDF (float DF (get-rounding-mode) rA)) +- () +- ) +- + (dni lf-itof-d32 + "lf.itof.d regpair/regpair" + ((MACH ORFPX64A32-MACHS)) +@@ -248,15 +218,6 @@ + () + ) + +-(dni lf-ftoi-d +- "lf.ftoi.d reg/reg" +- ((MACH ORFPX64-MACHS)) +- "lf.ftoi.d $rD,$rADF" +- (+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D) +- (set WI rD (fix WI (get-rounding-mode) rADF)) +- () +- ) +- + (dni lf-ftoi-d32 + "lf.ftoi.d regpair/regpair" + ((MACH ORFPX64A32-MACHS)) +@@ -276,14 +237,6 @@ + (symantics rtx-mnemonic SF rASF rBSF) + () + ) +- (dni (.sym lf-sf mnemonic -d) +- (.str "lf.sf" mnemonic ".d reg/reg") +- ((MACH ORFPX64-MACHS)) +- (.str "lf.sf" mnemonic ".d $rADF,$rBDF") +- (+ OPC_FLOAT (f-r1 0) rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D)) +- (symantics rtx-mnemonic DF rADF rBDF) +- () +- ) + (dni (.sym lf-sf mnemonic -d32) + (.str "lf.sf" mnemonic ".d regpair/regpair") + ((MACH ORFPX64A32-MACHS)) +@@ -336,15 +289,6 @@ + () + ) + +-(dni lf-madd-d +- "lf.madd.d reg/reg/reg" +- ((MACH ORFPX64-MACHS)) +- "lf.madd.d $rDDF,$rADF,$rBDF" +- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D) +- (set DF rDDF (add DF (mul DF rADF rBDF) rDDF)) +- () +- ) +- + (dni lf-madd-d32 + "lf.madd.d regpair/regpair/regpair" + ((MACH ORFPX64A32-MACHS)) +@@ -364,14 +308,6 @@ + (nop) + () + ) +- (dni (.sym "lf-cust" cust-num "-d") +- (.str "lf.cust" cust-num ".d") +- ((MACH ORFPX64-MACHS)) +- (.str "lf.cust" cust-num ".d") +- (+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D")) +- (nop) +- () +- ) + (dni (.sym "lf-cust" cust-num "-d32") + (.str "lf.cust" cust-num ".d") + ((MACH ORFPX64A32-MACHS)) +-- +2.21.0 + + diff --git a/patches/binutils-2.33.1/0003-or1k-32bithost-2.diff b/patches/binutils-2.33.1/0003-or1k-32bithost-2.diff new file mode 100644 index 0000000..7716879 --- /dev/null +++ b/patches/binutils-2.33.1/0003-or1k-32bithost-2.diff @@ -0,0 +1,4308 @@ +From: Stafford Horne +To: GNU Binutils +Cc: Openrisc , dalias@libc.org, Stafford Horne +Subject: [PATCH 2/2] or1k: Regnerate opcode files after removing 64-bit support +Date: Wed, 11 Dec 2019 06:49:06 +0900 + +opcodes/ChangeLog: + +yyyy-mm-dd Stafford Horne + + * or1k-asm.c: Regenerate. + * or1k-desc.c: Regenerate. + * or1k-desc.h: Regenerate. + * or1k-dis.c: Regenerate. + * or1k-ibld.c: Regenerate. + * or1k-opc.c: Regenerate. + * or1k-opc.h: Regenerate. + * or1k-opinst.c: Regenerate. +--- + opcodes/or1k-asm.c | 9 - + opcodes/or1k-desc.c | 1811 +++++++++++++++++++---------------------- + opcodes/or1k-desc.h | 332 ++++---- + opcodes/or1k-dis.c | 9 - + opcodes/or1k-ibld.c | 60 +- + opcodes/or1k-opc.c | 152 ---- + opcodes/or1k-opc.h | 28 +- + opcodes/or1k-opinst.c | 428 +++++----- + 8 files changed, 1182 insertions(+), 1647 deletions(-) + +diff --git a/opcodes/or1k-asm.c b/opcodes/or1k-asm.c +index 55668afee5..11f25868bb 100644 +--- a/opcodes/or1k-asm.c ++++ b/opcodes/or1k-asm.c +@@ -519,9 +519,6 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd, + case OR1K_OPERAND_RAD32F : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RAD32F, (unsigned long *) (& fields->f_rad32)); + break; +- case OR1K_OPERAND_RADF : +- errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r2); +- break; + case OR1K_OPERAND_RADI : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RADI, (unsigned long *) (& fields->f_rad32)); + break; +@@ -534,9 +531,6 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd, + case OR1K_OPERAND_RBD32F : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RBD32F, (unsigned long *) (& fields->f_rbd32)); + break; +- case OR1K_OPERAND_RBDF : +- errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r3); +- break; + case OR1K_OPERAND_RBDI : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RBDI, (unsigned long *) (& fields->f_rbd32)); + break; +@@ -549,9 +543,6 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd, + case OR1K_OPERAND_RDD32F : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RDD32F, (unsigned long *) (& fields->f_rdd32)); + break; +- case OR1K_OPERAND_RDDF : +- errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1); +- break; + case OR1K_OPERAND_RDDI : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RDDI, (unsigned long *) (& fields->f_rdd32)); + break; +diff --git a/opcodes/or1k-desc.c b/opcodes/or1k-desc.c +index 3357849a27..10158cd076 100644 +--- a/opcodes/or1k-desc.c ++++ b/opcodes/or1k-desc.c +@@ -49,8 +49,6 @@ static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = + { "base", MACH_BASE }, + { "or32", MACH_OR32 }, + { "or32nd", MACH_OR32ND }, +- { "or64", MACH_OR64 }, +- { "or64nd", MACH_OR64ND }, + { "max", MACH_MAX }, + { 0, 0 } + }; +@@ -129,8 +127,6 @@ static const CGEN_ISA or1k_cgen_isa_table[] = { + static const CGEN_MACH or1k_cgen_mach_table[] = { + { "or32", "or1k", MACH_OR32, 0 }, + { "or32nd", "or1knd", MACH_OR32ND, 0 }, +- { "or64", "or1k64", MACH_OR64, 0 }, +- { "or64nd", "or1k64nd", MACH_OR64ND, 0 }, + { 0, 0, 0, 0 } + }; + +@@ -226,52 +222,6 @@ CGEN_KEYWORD or1k_cgen_opval_h_fsr = + 0, 0, 0, 0, "" + }; + +-static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] = +-{ +- { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, +- { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, +- { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, +- { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, +- { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, +- { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, +- { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, +- { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, +- { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, +- { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, +- { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, +- { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, +- { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, +- { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, +- { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, +- { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, +- { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, +- { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, +- { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, +- { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, +- { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, +- { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, +- { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, +- { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, +- { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, +- { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, +- { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, +- { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, +- { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, +- { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, +- { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, +- { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, +- { "lr", 9, {0, {{{0, 0}}}}, 0, 0 }, +- { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, +- { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } +-}; +- +-CGEN_KEYWORD or1k_cgen_opval_h_fdr = +-{ +- & or1k_cgen_opval_h_fdr_entries[0], +- 35, +- 0, 0, 0, 0, "" +-}; +- + + /* The hardware table. */ + +@@ -284,642 +234,641 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] = + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<f_rad32, 0|(1<f_r2, 0); +- break; + case OR1K_OPERAND_RADI : + print_regpair (cd, info, fields->f_rad32, 0|(1<f_rbd32, 0|(1<f_r3, 0); +- break; + case OR1K_OPERAND_RBDI : + print_regpair (cd, info, fields->f_rbd32, 0|(1<f_rdd32, 0|(1<f_r1, 0); +- break; + case OR1K_OPERAND_RDDI : + print_regpair (cd, info, fields->f_rdd32, 0|(1<f_disp21; +- value = ((((DI) (value) >> (13))) - (((DI) (pc) >> (13)))); ++ value = ((((SI) (value) >> (13))) - (((SI) (pc) >> (13)))); + errmsg = insert_normal (cd, value, 0|(1<f_disp26; +- value = ((DI) (((value) - (pc))) >> (2)); ++ value = ((SI) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_r2, 0, 0, 20, 5, 32, total_length, buffer); +- break; + case OR1K_OPERAND_RADI : + { + { +@@ -641,9 +638,6 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd, + break; + } + break; +- case OR1K_OPERAND_RBDF : +- errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); +- break; + case OR1K_OPERAND_RBDI : + { + { +@@ -678,9 +672,6 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd, + break; + } + break; +- case OR1K_OPERAND_RDDF : +- errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); +- break; + case OR1K_OPERAND_RDDI : + { + { +@@ -783,7 +774,7 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd, + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (13))))) << (13)); ++ value = ((((value) + (((SI) (pc) >> (13))))) << (13)); + fields->f_disp21 = value; + } + break; +@@ -807,9 +798,6 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd, + FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5)))); + } + break; +- case OR1K_OPERAND_RADF : +- length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); +- break; + case OR1K_OPERAND_RADI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); +@@ -834,9 +822,6 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd, + FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5)))); + } + break; +- case OR1K_OPERAND_RBDF : +- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); +- break; + case OR1K_OPERAND_RBDI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); +@@ -861,9 +846,6 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd, + FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5)))); + } + break; +- case OR1K_OPERAND_RDDF : +- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); +- break; + case OR1K_OPERAND_RDDI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); +@@ -954,9 +936,6 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RAD32F : + value = fields->f_rad32; + break; +- case OR1K_OPERAND_RADF : +- value = fields->f_r2; +- break; + case OR1K_OPERAND_RADI : + value = fields->f_rad32; + break; +@@ -969,9 +948,6 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RBD32F : + value = fields->f_rbd32; + break; +- case OR1K_OPERAND_RBDF : +- value = fields->f_r3; +- break; + case OR1K_OPERAND_RBDI : + value = fields->f_rbd32; + break; +@@ -984,9 +960,6 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RDD32F : + value = fields->f_rdd32; + break; +- case OR1K_OPERAND_RDDF : +- value = fields->f_r1; +- break; + case OR1K_OPERAND_RDDI : + value = fields->f_rdd32; + break; +@@ -1041,9 +1014,6 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RAD32F : + value = fields->f_rad32; + break; +- case OR1K_OPERAND_RADF : +- value = fields->f_r2; +- break; + case OR1K_OPERAND_RADI : + value = fields->f_rad32; + break; +@@ -1056,9 +1026,6 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RBD32F : + value = fields->f_rbd32; + break; +- case OR1K_OPERAND_RBDF : +- value = fields->f_r3; +- break; + case OR1K_OPERAND_RBDI : + value = fields->f_rbd32; + break; +@@ -1071,9 +1038,6 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RDD32F : + value = fields->f_rdd32; + break; +- case OR1K_OPERAND_RDDF : +- value = fields->f_r1; +- break; + case OR1K_OPERAND_RDDI : + value = fields->f_rdd32; + break; +@@ -1135,9 +1099,6 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RAD32F : + fields->f_rad32 = value; + break; +- case OR1K_OPERAND_RADF : +- fields->f_r2 = value; +- break; + case OR1K_OPERAND_RADI : + fields->f_rad32 = value; + break; +@@ -1150,9 +1111,6 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RBD32F : + fields->f_rbd32 = value; + break; +- case OR1K_OPERAND_RBDF : +- fields->f_r3 = value; +- break; + case OR1K_OPERAND_RBDI : + fields->f_rbd32 = value; + break; +@@ -1165,9 +1123,6 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RDD32F : + fields->f_rdd32 = value; + break; +- case OR1K_OPERAND_RDDF : +- fields->f_r1 = value; +- break; + case OR1K_OPERAND_RDDI : + fields->f_rdd32 = value; + break; +@@ -1219,9 +1174,6 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RAD32F : + fields->f_rad32 = value; + break; +- case OR1K_OPERAND_RADF : +- fields->f_r2 = value; +- break; + case OR1K_OPERAND_RADI : + fields->f_rad32 = value; + break; +@@ -1234,9 +1186,6 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RBD32F : + fields->f_rbd32 = value; + break; +- case OR1K_OPERAND_RBDF : +- fields->f_r3 = value; +- break; + case OR1K_OPERAND_RBDI : + fields->f_rbd32 = value; + break; +@@ -1249,9 +1198,6 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RDD32F : + fields->f_rdd32 = value; + break; +- case OR1K_OPERAND_RDDF : +- fields->f_r1 = value; +- break; + case OR1K_OPERAND_RDDI : + fields->f_rdd32 = value; + break; +diff --git a/opcodes/or1k-opc.c b/opcodes/or1k-opc.c +index 86e421099a..c390f85e52 100644 +--- a/opcodes/or1k-opc.c ++++ b/opcodes/or1k-opc.c +@@ -163,10 +163,6 @@ static const CGEN_IFMT ifmt_lf_add_s ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + }; + +-static const CGEN_IFMT ifmt_lf_add_d ATTRIBUTE_UNUSED = { +- 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +-}; +- + static const CGEN_IFMT ifmt_lf_add_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0000ff, { { F (F_OPCODE) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } } + }; +@@ -175,10 +171,6 @@ static const CGEN_IFMT ifmt_lf_itof_s ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + }; + +-static const CGEN_IFMT ifmt_lf_itof_d ATTRIBUTE_UNUSED = { +- 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +-}; +- + static const CGEN_IFMT ifmt_lf_itof_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00f9ff, { { F (F_OPCODE) }, { F (F_R3) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RESV_8_1) }, { F (F_OP_7_8) }, { 0 } } + }; +@@ -187,10 +179,6 @@ static const CGEN_IFMT ifmt_lf_ftoi_s ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + }; + +-static const CGEN_IFMT ifmt_lf_ftoi_d ATTRIBUTE_UNUSED = { +- 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +-}; +- + static const CGEN_IFMT ifmt_lf_ftoi_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00f9ff, { { F (F_OPCODE) }, { F (F_R3) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RESV_8_1) }, { F (F_OP_7_8) }, { 0 } } + }; +@@ -199,10 +187,6 @@ static const CGEN_IFMT ifmt_lf_sfeq_s ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + }; + +-static const CGEN_IFMT ifmt_lf_sfeq_d ATTRIBUTE_UNUSED = { +- 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +-}; +- + static const CGEN_IFMT ifmt_lf_sfeq_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe004ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_RESV_10_1) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } } + }; +@@ -211,10 +195,6 @@ static const CGEN_IFMT ifmt_lf_cust1_s ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + }; + +-static const CGEN_IFMT ifmt_lf_cust1_d ATTRIBUTE_UNUSED = { +- 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +-}; +- + static const CGEN_IFMT ifmt_lf_cust1_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe004ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_RESV_10_1) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } } + }; +@@ -828,12 +808,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000000 } + }, +-/* lf.add.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000010 } +- }, + /* lf.add.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -846,12 +820,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000001 } + }, +-/* lf.sub.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000011 } +- }, + /* lf.sub.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -864,12 +832,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000002 } + }, +-/* lf.mul.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000012 } +- }, + /* lf.mul.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -882,12 +844,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000003 } + }, +-/* lf.div.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000013 } +- }, + /* lf.div.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -900,12 +856,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000006 } + }, +-/* lf.rem.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000016 } +- }, + /* lf.rem.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -918,12 +868,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RA), 0 } }, + & ifmt_lf_itof_s, { 0xc8000004 } + }, +-/* lf.itof.d $rDDF,$rA */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RA), 0 } }, +- & ifmt_lf_itof_d, { 0xc8000014 } +- }, + /* lf.itof.d $rDD32F,$rADI */ + { + { 0, 0, 0, 0 }, +@@ -936,12 +880,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RD), ',', OP (RASF), 0 } }, + & ifmt_lf_ftoi_s, { 0xc8000005 } + }, +-/* lf.ftoi.d $rD,$rADF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RD), ',', OP (RADF), 0 } }, +- & ifmt_lf_ftoi_d, { 0xc8000015 } +- }, + /* lf.ftoi.d $rDDI,$rAD32F */ + { + { 0, 0, 0, 0 }, +@@ -954,12 +892,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc8000008 } + }, +-/* lf.sfeq.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc8000018 } +- }, + /* lf.sfeq.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -972,12 +904,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc8000009 } + }, +-/* lf.sfne.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc8000019 } +- }, + /* lf.sfne.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -990,12 +916,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800000b } + }, +-/* lf.sfge.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800001b } +- }, + /* lf.sfge.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1008,12 +928,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800000a } + }, +-/* lf.sfgt.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800001a } +- }, + /* lf.sfgt.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1026,12 +940,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800000c } + }, +-/* lf.sflt.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800001c } +- }, + /* lf.sflt.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1044,12 +952,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800000d } + }, +-/* lf.sfle.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800001d } +- }, + /* lf.sfle.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1062,12 +964,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc8000028 } + }, +-/* lf.sfueq.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc8000038 } +- }, + /* lf.sfueq.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1080,12 +976,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc8000029 } + }, +-/* lf.sfune.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc8000039 } +- }, + /* lf.sfune.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1098,12 +988,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002a } + }, +-/* lf.sfugt.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800003a } +- }, + /* lf.sfugt.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1116,12 +1000,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002b } + }, +-/* lf.sfuge.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800003b } +- }, + /* lf.sfuge.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1134,12 +1012,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002c } + }, +-/* lf.sfult.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800003c } +- }, + /* lf.sfult.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1152,12 +1024,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002d } + }, +-/* lf.sfule.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800003d } +- }, + /* lf.sfule.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1170,12 +1036,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002e } + }, +-/* lf.sfun.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800003e } +- }, + /* lf.sfun.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1188,12 +1048,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000007 } + }, +-/* lf.madd.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000017 } +- }, + /* lf.madd.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1206,12 +1060,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_cust1_s, { 0xc80000d0 } + }, +-/* lf.cust1.d */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, 0 } }, +- & ifmt_lf_cust1_d, { 0xc80000e0 } +- }, + /* lf.cust1.d */ + { + { 0, 0, 0, 0 }, +diff --git a/opcodes/or1k-opc.h b/opcodes/or1k-opc.h +index 2ec4b4b323..0c392274a2 100644 +--- a/opcodes/or1k-opc.h ++++ b/opcodes/or1k-opc.h +@@ -70,23 +70,17 @@ typedef enum cgen_insn_type { + , OR1K_INSN_L_MACU, OR1K_INSN_L_MSB, OR1K_INSN_L_MSBU, OR1K_INSN_L_CUST1 + , OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3, OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5 + , OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7, OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S +- , OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_ADD_D32, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D +- , OR1K_INSN_LF_SUB_D32, OR1K_INSN_LF_MUL_S, OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_MUL_D32 +- , OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_DIV_D32, OR1K_INSN_LF_REM_S +- , OR1K_INSN_LF_REM_D, OR1K_INSN_LF_REM_D32, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D +- , OR1K_INSN_LF_ITOF_D32, OR1K_INSN_LF_FTOI_S, OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_FTOI_D32 +- , OR1K_INSN_LF_SFEQ_S, OR1K_INSN_LF_SFEQ_D, OR1K_INSN_LF_SFEQ_D32, OR1K_INSN_LF_SFNE_S +- , OR1K_INSN_LF_SFNE_D, OR1K_INSN_LF_SFNE_D32, OR1K_INSN_LF_SFGE_S, OR1K_INSN_LF_SFGE_D +- , OR1K_INSN_LF_SFGE_D32, OR1K_INSN_LF_SFGT_S, OR1K_INSN_LF_SFGT_D, OR1K_INSN_LF_SFGT_D32 +- , OR1K_INSN_LF_SFLT_S, OR1K_INSN_LF_SFLT_D, OR1K_INSN_LF_SFLT_D32, OR1K_INSN_LF_SFLE_S +- , OR1K_INSN_LF_SFLE_D, OR1K_INSN_LF_SFLE_D32, OR1K_INSN_LF_SFUEQ_S, OR1K_INSN_LF_SFUEQ_D +- , OR1K_INSN_LF_SFUEQ_D32, OR1K_INSN_LF_SFUNE_S, OR1K_INSN_LF_SFUNE_D, OR1K_INSN_LF_SFUNE_D32 +- , OR1K_INSN_LF_SFUGT_S, OR1K_INSN_LF_SFUGT_D, OR1K_INSN_LF_SFUGT_D32, OR1K_INSN_LF_SFUGE_S +- , OR1K_INSN_LF_SFUGE_D, OR1K_INSN_LF_SFUGE_D32, OR1K_INSN_LF_SFULT_S, OR1K_INSN_LF_SFULT_D +- , OR1K_INSN_LF_SFULT_D32, OR1K_INSN_LF_SFULE_S, OR1K_INSN_LF_SFULE_D, OR1K_INSN_LF_SFULE_D32 +- , OR1K_INSN_LF_SFUN_S, OR1K_INSN_LF_SFUN_D, OR1K_INSN_LF_SFUN_D32, OR1K_INSN_LF_MADD_S +- , OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_MADD_D32, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D +- , OR1K_INSN_LF_CUST1_D32 ++ , OR1K_INSN_LF_ADD_D32, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D32, OR1K_INSN_LF_MUL_S ++ , OR1K_INSN_LF_MUL_D32, OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D32, OR1K_INSN_LF_REM_S ++ , OR1K_INSN_LF_REM_D32, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D32, OR1K_INSN_LF_FTOI_S ++ , OR1K_INSN_LF_FTOI_D32, OR1K_INSN_LF_SFEQ_S, OR1K_INSN_LF_SFEQ_D32, OR1K_INSN_LF_SFNE_S ++ , OR1K_INSN_LF_SFNE_D32, OR1K_INSN_LF_SFGE_S, OR1K_INSN_LF_SFGE_D32, OR1K_INSN_LF_SFGT_S ++ , OR1K_INSN_LF_SFGT_D32, OR1K_INSN_LF_SFLT_S, OR1K_INSN_LF_SFLT_D32, OR1K_INSN_LF_SFLE_S ++ , OR1K_INSN_LF_SFLE_D32, OR1K_INSN_LF_SFUEQ_S, OR1K_INSN_LF_SFUEQ_D32, OR1K_INSN_LF_SFUNE_S ++ , OR1K_INSN_LF_SFUNE_D32, OR1K_INSN_LF_SFUGT_S, OR1K_INSN_LF_SFUGT_D32, OR1K_INSN_LF_SFUGE_S ++ , OR1K_INSN_LF_SFUGE_D32, OR1K_INSN_LF_SFULT_S, OR1K_INSN_LF_SFULT_D32, OR1K_INSN_LF_SFULE_S ++ , OR1K_INSN_LF_SFULE_D32, OR1K_INSN_LF_SFUN_S, OR1K_INSN_LF_SFUN_D32, OR1K_INSN_LF_MADD_S ++ , OR1K_INSN_LF_MADD_D32, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D32 + } CGEN_INSN_TYPE; + + /* Index of `invalid' insn place holder. */ +diff --git a/opcodes/or1k-opinst.c b/opcodes/or1k-opinst.c +index 84a0dfe9bc..7be3e5210d 100644 +--- a/opcodes/or1k-opinst.c ++++ b/opcodes/or1k-opinst.c +@@ -43,54 +43,54 @@ static const CGEN_OPINST sfmt_empty_ops[] ATTRIBUTE_UNUSED = { + }; + + static const CGEN_OPINST sfmt_l_j_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, 0 }, +- { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP26), 0, 0 }, ++ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_adrp_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "disp21", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP21), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "disp21", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP21), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_jal_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, 0 }, +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "h_gpr_UDI_9", HW_H_GPR, CGEN_MODE_UDI, 0, 9, 0 }, +- { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP26), 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "h_gpr_USI_9", HW_H_GPR, CGEN_MODE_USI, 0, 9, 0 }, ++ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_jr_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_jalr_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "h_gpr_UDI_9", HW_H_GPR, CGEN_MODE_UDI, 0, 9, 0 }, +- { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "h_gpr_USI_9", HW_H_GPR, CGEN_MODE_USI, 0, 9, 0 }, ++ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_bnf_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, COND_REF }, +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, ++ { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP26), 0, COND_REF }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_trap_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +@@ -105,94 +105,94 @@ static const CGEN_OPINST sfmt_l_nop_imm_ops[] ATTRIBUTE_UNUSED = { + + static const CGEN_OPINST sfmt_l_movhi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_macrc_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_mfspr_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_mtspr_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, + { INPUT, "uimm16_split", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16_SPLIT), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lwz_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lws_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_SI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lwa_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, + { OUTPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lbz_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_UQI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lbs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_QI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lhz_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_UHI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_2", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lhs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_HI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_sw_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, + { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, + { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 }, +@@ -201,8 +201,8 @@ static const CGEN_OPINST sfmt_l_sw_ops[] ATTRIBUTE_UNUSED = { + + static const CGEN_OPINST sfmt_l_sb_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, + { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, + { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UQI_addr", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 }, +@@ -211,8 +211,8 @@ static const CGEN_OPINST sfmt_l_sb_ops[] ATTRIBUTE_UNUSED = { + + static const CGEN_OPINST sfmt_l_sh_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, + { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, + { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_addr", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 }, +@@ -222,228 +222,228 @@ static const CGEN_OPINST sfmt_l_sh_ops[] ATTRIBUTE_UNUSED = { + static const CGEN_OPINST sfmt_l_swa_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, +- { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, COND_REF }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_sll_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_slli_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "uimm6", HW_H_UIMM6, CGEN_MODE_UINT, OP_ENT (UIMM6), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_and_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_add_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_addc_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_mul_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_muld_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_mulu_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_div_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, COND_REF }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, COND_REF }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_divu_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, COND_REF }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, COND_REF }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_ff1_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_xori_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_addi_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_addic_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_muli_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_exths_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_cmov_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF }, +- { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, COND_REF }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, COND_REF }, ++ { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_sfgts_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_sfgtsi_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_mac_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_maci_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_macu_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +@@ -454,13 +454,6 @@ static const CGEN_OPINST sfmt_lf_add_s_ops[] ATTRIBUTE_UNUSED = { + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +-static const CGEN_OPINST sfmt_lf_add_d_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, +- { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 }, +- { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, +- { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +-}; +- + static const CGEN_OPINST sfmt_lf_add_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, +@@ -469,43 +462,29 @@ static const CGEN_OPINST sfmt_lf_add_d32_ops[] ATTRIBUTE_UNUSED = { + }; + + static const CGEN_OPINST sfmt_lf_itof_s_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +-static const CGEN_OPINST sfmt_lf_itof_d_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, +- { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +-}; +- + static const CGEN_OPINST sfmt_lf_itof_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rADI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RADI), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_lf_ftoi_s_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +-}; +- +-static const CGEN_OPINST sfmt_lf_ftoi_d_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_lf_ftoi_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "rDDI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RDDI), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; +@@ -513,21 +492,14 @@ static const CGEN_OPINST sfmt_lf_ftoi_d32_ops[] ATTRIBUTE_UNUSED = { + static const CGEN_OPINST sfmt_lf_sfeq_s_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, + { INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, +- { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +-}; +- +-static const CGEN_OPINST sfmt_lf_sfeq_d_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, +- { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_lf_sfeq_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +@@ -539,14 +511,6 @@ static const CGEN_OPINST sfmt_lf_madd_s_ops[] ATTRIBUTE_UNUSED = { + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +-static const CGEN_OPINST sfmt_lf_madd_d_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, +- { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 }, +- { INPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, +- { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, +- { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +-}; +- + static const CGEN_OPINST sfmt_lf_madd_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, +@@ -664,71 +628,49 @@ static const CGEN_OPINST *or1k_cgen_opinst_table[MAX_INSNS] = { + & sfmt_l_msync_ops[0], + & sfmt_l_msync_ops[0], + & sfmt_lf_add_s_ops[0], +- & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], + & sfmt_lf_add_s_ops[0], +- & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], + & sfmt_lf_add_s_ops[0], +- & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], + & sfmt_lf_add_s_ops[0], +- & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], + & sfmt_lf_add_s_ops[0], +- & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], + & sfmt_lf_itof_s_ops[0], +- & sfmt_lf_itof_d_ops[0], + & sfmt_lf_itof_d32_ops[0], + & sfmt_lf_ftoi_s_ops[0], +- & sfmt_lf_ftoi_d_ops[0], + & sfmt_lf_ftoi_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_madd_s_ops[0], +- & sfmt_lf_madd_d_ops[0], + & sfmt_lf_madd_d32_ops[0], + & sfmt_l_msync_ops[0], + & sfmt_l_msync_ops[0], +- & sfmt_l_msync_ops[0], + }; + + /* Function to call before using the operand instance table. */ +-- +2.21.0 + +