423ec28bb8
During SPL boot several Clock Controller Module (CCM) registers are read, most important are PLL and Tuning, as well as divisor registers. This patch adds these registers and initializes reset values from user's guide. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20221226220303.14420-2-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48 lines
1.1 KiB
C
48 lines
1.1 KiB
C
#ifndef HW_ARM_ALLWINNER_A10_H
|
|
#define HW_ARM_ALLWINNER_A10_H
|
|
|
|
#include "qemu/error-report.h"
|
|
#include "hw/char/serial.h"
|
|
#include "hw/arm/boot.h"
|
|
#include "hw/pci/pci_device.h"
|
|
#include "hw/timer/allwinner-a10-pit.h"
|
|
#include "hw/intc/allwinner-a10-pic.h"
|
|
#include "hw/net/allwinner_emac.h"
|
|
#include "hw/sd/allwinner-sdhost.h"
|
|
#include "hw/ide/ahci.h"
|
|
#include "hw/usb/hcd-ohci.h"
|
|
#include "hw/usb/hcd-ehci.h"
|
|
#include "hw/rtc/allwinner-rtc.h"
|
|
#include "hw/misc/allwinner-a10-ccm.h"
|
|
|
|
#include "target/arm/cpu.h"
|
|
#include "qom/object.h"
|
|
|
|
|
|
#define AW_A10_SDRAM_BASE 0x40000000
|
|
|
|
#define AW_A10_NUM_USB 2
|
|
|
|
#define TYPE_AW_A10 "allwinner-a10"
|
|
OBJECT_DECLARE_SIMPLE_TYPE(AwA10State, AW_A10)
|
|
|
|
struct AwA10State {
|
|
/*< private >*/
|
|
DeviceState parent_obj;
|
|
/*< public >*/
|
|
|
|
ARMCPU cpu;
|
|
AwA10ClockCtlState ccm;
|
|
AwA10PITState timer;
|
|
AwA10PICState intc;
|
|
AwEmacState emac;
|
|
AllwinnerAHCIState sata;
|
|
AwSdHostState mmc0;
|
|
AwRtcState rtc;
|
|
MemoryRegion sram_a;
|
|
EHCISysBusState ehci[AW_A10_NUM_USB];
|
|
OHCISysBusState ohci[AW_A10_NUM_USB];
|
|
};
|
|
|
|
#endif
|