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FRET-qemu/target/riscv
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Peter Maydell 3d3d399e76 target/riscv: Set default NaN pattern explicitly 
Set the default NaN pattern explicitly for riscv.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
2024-12-11 15:31:07 +00:00
..
insn_trans
target/riscv: Set vdata.vm field for vector load/store whole register instructions
2024-11-07 08:21:14 +10:00
kvm
target/riscv/kvm: Update kvm exts to Linux v6.11
2024-11-07 12:33:44 +10:00
tcg
target/riscv: AMO operations always raise store/AMO fault
2024-10-30 11:22:08 +10:00
arch_dump.c
target/riscv: Fix format for comments
2023-05-05 10:49:50 +10:00
bitmanip_helper.c
target/riscv: rvk: add support for zbkx extension
2022-04-29 10:47:45 +10:00
common-semi-target.h
semihosting: Split out common-semi-target.h
2022-06-28 04:35:07 +05:30
cpu_bits.h
target/riscv: implement zicfiss instructions
2024-10-30 11:22:08 +10:00
cpu_cfg.h
target/riscv: Add zicfiss extension
2024-10-30 11:22:08 +10:00
cpu_helper.c
target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()
2024-12-03 12:26:24 +01:00
cpu_user.h
target/riscv: zicfilp lpad impl and branch tracking
2024-10-30 11:22:08 +10:00
cpu_vendorid.h
target/riscv: add Ventana's Veyron V1 CPU
2023-05-05 10:49:50 +10:00
cpu-param.h
license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later
2024-09-20 10:11:59 +03:00
cpu-qom.h
target/riscv: Add max32 CPU for RV64 QEMU
2024-10-30 11:22:07 +10:00
cpu.c
target/riscv: Set default NaN pattern explicitly
2024-12-11 15:31:07 +00:00
cpu.h
target/riscv: AMO operations always raise store/AMO fault
2024-10-30 11:22:08 +10:00
crypto_helper.c
target/riscv: Use accelerated helper for AES64KS1I
2023-09-11 11:45:55 +10:00
csr.c
target/riscv: introduce ssp and enabling controls for zicfiss
2024-10-30 11:22:08 +10:00
debug.c
target/riscv: Add textra matching condition for the triggers
2024-10-02 15:11:51 +10:00
debug.h
target/riscv: Add textra matching condition for the triggers
2024-10-02 15:11:51 +10:00
fpu_helper.c
target/riscv: Fix froundnx.h nanbox check
2024-06-26 23:02:35 +10:00
gdbstub.c
riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
2024-06-03 11:12:12 +10:00
helper.h
target/riscv: Raise exceptions on wrs.nto
2024-06-03 11:12:11 +10:00
insn16.decode
target/riscv: compressed encodings for sspush and sspopchk
2024-10-30 11:22:08 +10:00
insn32.decode
target/riscv: implement zicfiss instructions
2024-10-30 11:22:08 +10:00
instmap.h
target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
2022-09-07 09:18:32 +02:00
internals.h
target/riscv: mmu changes for zicfiss shadow stack protection
2024-10-30 11:22:08 +10:00
Kconfig
target/riscv/cpu_helper: Fix linking problem with semihosting disabled
2024-10-02 15:11:51 +10:00
m128_helper.c
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
2023-08-31 19:47:43 +02:00
machine.c
target/riscv: introduce ssp and enabling controls for zicfiss
2024-10-30 11:22:08 +10:00
meson.build
riscv: thead: Add th.sxstatus CSR emulation
2024-06-03 11:12:12 +10:00
monitor.c
target/riscv: remove break after g_assert_not_reached()
2024-09-24 13:53:35 +02:00
op_helper.c
target/riscv: save and restore elp state on priv transitions
2024-10-30 11:22:08 +10:00
pmp.c
target/riscv: Introduce elp state and enabling controls for zicfilp
2024-10-30 11:22:08 +10:00
pmp.h
target/riscv: Introduce elp state and enabling controls for zicfilp
2024-10-30 11:22:08 +10:00
pmu.c
target/riscv: Add asserts for out-of-bound access
2024-08-06 14:20:16 +10:00
pmu.h
target/riscv: More accurately model priv mode filtering.
2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c
target: Improve error reporting for CpuModelInfo member @props
2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h
target/riscv/kvm: implement SBI debug console (DBCN) calls
2024-06-03 11:12:11 +10:00
th_csr.c
riscv: thead: Add th.sxstatus CSR emulation
2024-06-03 11:12:12 +10:00
time_helper.c
target/riscv: Stop timer with infinite timecmp
2024-10-02 15:11:51 +10:00
time_helper.h
target/riscv: Simplify type conversion for CPURISCVState
2023-05-05 10:49:49 +10:00
trace-events
target/riscv: Add ePMP CSR access functions
2021-05-11 20:02:06 +10:00
trace.h
trace: switch position of headers to what Meson requires
2020-08-21 06:18:24 -04:00
translate.c
target/riscv: implement zicfiss instructions
2024-10-30 11:22:08 +10:00
vcrypto_helper.c
target/riscv/vector_helpers: do early exit when vstart >= vl
2024-03-22 15:20:02 +10:00
vector_helper.c
target/riscv: Inline unit-stride ld/st and corresponding functions for performance
2024-11-07 12:33:44 +10:00
vector_internals.c
target/riscv: Fix the element agnostic function problem
2024-06-03 11:12:12 +10:00
vector_internals.h
target/riscv/vector_helpers: do early exit when vstart >= vl
2024-03-22 15:20:02 +10:00
xthead.decode
RISC-V: Adding XTheadFmv ISA extension
2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode
target/riscv: Add XVentanaCondOps custom extension
2022-02-16 12:24:18 +10:00
zce_helper.c
target/riscv: add support for Zcmt extension
2023-05-05 10:49:50 +10:00